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Xilinx UG181 manual Static Timing Analysis, Generating a Bitstream, Xilinx Tool Flow

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Static Timing Analysis

To evaluate timing closure on a design and create a timing report file (TWR) derived from static timing analysis of the physical design file (NCD), the trce command must be executed. The analysis is typically based on constraints included in the optional physical constraints file (PCF). An example of the trce command is provided below:

trce -e 10 routed.ncd mapped.pcf -o routed.twr

The trce command outputs a routed.twr file, which performs timing analysis of the placed and routed design based on the user constraints.

Timing Simulation

After the user design is functionally correct and meets all timing constraints, it is recommended the user perform back-annotated timing simulation to verify that the entire user design will function correctly before the user tests their design in hardware. The netgen command is used to generate a post-par simulation model, which includes all timing information. An example of the netgen command is provided below:

netgen -sim -ofmt <vhdl verilog> routed.ncd

The netgen command outputs routed.v[hd] and routed.sdf files, which allow the user to run timing simulation.

Generating a Bitstream

To create the configuration (BIT) file based on the contents of a physical implementation file (NCD), the bitgen command must be executed. The BIT file defines the behavior of the programmed FPGA. An example of the bitgen command is provided below:

bitgen -w routed.ncd

Note the user should take care in setting the required bitgen options, including selection of the startup clock. See the Development System Reference Guide for details.

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual Static Timing Analysis, Generating a Bitstream, Xilinx Tool Flow

Contents

UG181 June 27 LogiCORE IP SPI-4.2 LiteDate Version Revision SPI-4.2 Lite v4.3 User Guide UG181 June 27Table of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide 1SPI-4.2 Lite Core in a Typical Link Layer Application Schedule of Figures30Addressable Status Fifo Interface 4-Channel Configuration Generating the Core Designing with the Core Schedule of TablesAppendix a SPI-4.2 Lite Control Word About This Guide ContentsTypographical ConventionsConventions Online DocumentPreface About This Guide About the Core IntroductionRecommended Design Experience Additional Core ResourcesFeedback Technical SupportSPI-4.2 Lite Core DocumentSystem Overview Core ArchitectureSink Core Source CoreCore Architecture Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram RCtlN Sink SPI-4.2 InterfaceSink Control and Status Interface Sink User InterfaceSink Fifo Interface 3Sink Fifo Signals NameCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate RDClk0 General Purpose Sink Clocking InterfaceRDClk0USER This clock Source Core InterfacesSource Core Interfaces Source SPI-4.2 InterfaceDomain Source User InterfaceSource Control and Status Interface 16 bytes with no EOP Name Direction Clock Description Domain Source Fifo Interface14 Source Status Fifo Signals Source Status Address Source Static Configuration InterfaceSource Almost Full Threshold Assert Source Calendar Period The SrcCalendarM Source Clocking InterfaceSysClk0 General Purpose Domain Core Architecture Core Generator Graphical User Interface Generating the CoreSink Status Options Screen Main ScreenComponent Name Core OptionsCalendar Flow ControlStatus Interface Sink Other Options Screen SynchronizationFifo Threshold Source Status Options Screen Clock ModeClocking Clock DistributionBursting Source Other Options ScreenBurst Size in Credits Burst ModeSysClk Distribution TSClk DistributionCalendar COE File Format Designing with the Core Understand Signal PipeliningGeneral Design Guidelines Know the Degree of DifficultyInitializing the SPI-4.2 Lite Core Recognize Timing Critical SignalsKeep it Registered Use Supported Design FlowsBasic Operation Sink CoreSPI-4.2 Interface Sink Data Path Example1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP Sink Fifo RCtlSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Almost Empty Sink Fifo Interface SignalsSink Almost Full Sink Fifo EmptySink Overflow Sink Status and Flow Control SignalsInitializing the Calendar In-Circuit Sink Calendar Initialization7Sink Calendar Initialization Sink Flow Control8Typical Flow Control Implementation for 4-Channel System 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3 Sink Status Fifo Interface ExampleSink Status Fifo Status Interface Example Insertion of DIP2 Errors Sink Static Configuration SignalsFifo Almost Full Mode FifoAFMode and Sink Almost Full12FIFO Almost Full Mode Sink Data Capture Implementation Fifo Almost Full Mode 10 orStatic Alignment DCM Alignment Implementation ConsiderationsSynchronization and Start-up Reset HuntSync Wait Sync Data Error HandlingSync Train In-Frame and Out-of-Frame BehaviorSink SPI-4.2 Bus Error and Sink Bus Error Status70 Sink Fifo Burst ErrorEOP Abort Handling Loss of RDClkSink DIP-4 Error Handling Sequential Payload Control WordsSequential End-of-Burst Control Words 18Example of Error Flag SnkFFDIP4Err Reserved Control Words Source CoreSource Core Source Data Path Example22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Inserting DIP4 Errors Source Control and Status SignalsTransmitting Idle Cycles Source Fifo Almost Full Source Fifo Interface Signals24Source Fifo Almost-full Condition Source Fifo OverflowSource Status and Flow Control Signals Insertion of DIP-4 ErrorsWriting to the Source Fifo 27Typical User Design Example Source Calendar Initialization28Source Calendar Initialization Source Flow Control Addressable Status Interface29Addressable Status Fifo Interface Addressable Status Fifo Interface Example30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Burst Mode Source Static Configuration Signals35Example Of Source Burst Mode = Source Burst Mode ExampleReset Source Behavior After Synchronization Source Behavior Before SynchronizationEOP Abort Insertion Source Out of FrameSource Pattern Error Handling Source DIP-2 Error HandlingSource Status Frame Word Handling Incorrect Burst TerminationDesigning with the Core Overview Constraining the CoreSink Core Required Constraints Timing ConstraintsTime Names for Clocks Maxdelay for ResetTimespecs for Clocks Constraining the CoreClock Delay in Iserdes Phase Shift for DCMDCM and Static Alignment Constraints Sink Core Required ConstraintsPlacement Placement ConstraintsSink Core Optional Constraints IDelayCtrlStandards Constraints IOB Register PackingArea Group Constraints Source Core Required ConstraintsTiming Ignore Constraints Timenames for ClocksSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsUser Constraints Constraints MigrationNew Target Region or Device Package Target Device Modifying the UCF FileSink Core Source CoreInst TSClk LOC = Bank3 Special Design Considerations Sink Clocking OptionsEmbedded Clocking Special Design Considerations User ClockingGlobal Clocking Sink Clocking Options2Sink Core User Clocking Resources Clocking Option 3Sink User Clocking Global Clocking Regional ClockingSource Clocking Options Source Clocking Options5Source Clocking Master and Slave Implementation Master ClockingIOB 8Source Clocking Regional Clocking for SysClk Slave Clocking 3SysClk Clocking Resources Clocking OptionTSClk Clocking Resources Clocking Option Instantiating Multiple Cores Multiple Core ImplementationsGenerating the Cores Creating Top-Level UCF FileMultiple Core Implementations Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Functional Simulation Simulating and Implementing the CoreGenerating a Simulation Model Generating a Simulation Model with Initialized CalendarSimulating and Implementing the Core Timing SimulationSynthesis of Example Design SynthesisSynplify SynthesisExample Design Script Xilinx Tool FlowNGDBuild Mapping the DesignStatic Timing Analysis Generating a BitstreamXilinx Tool Flow 130 Eops SPI-4.2 Lite Control WordDIP-4 Example SPI-4.2 Lite Calendar ProgrammingAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification