Xilinx UG181 manual Domain

Source Core Interfaces

R

Table 2-17:Source Core Clock Status Signals: Master Configuration (Continued)

Signal Name	Direction	Clock	Description
		Domain
DCMLost_TDClk	Output	N/A	Indicates TDClk input has stopped (status
			bit one of TDClk DCM)
SrcClksRdy	Output	N/A	Indicates all Source core clocks are ready
			for use.

Table 2-18:Source Core Clocks: Slave Configuration

Clock Pins	Direction	Description	Max Freq.
SysClk0_GBSLV	Input	SysClk0: This clock is	Virtex-5: 275 MHz
	(user interface)	used to clock the internal	Virtex-4: 190 MHz
		source core logic.
			Virtex-II Pro: 160 MHz
			Virtex-II: 160 MHz
			Spartan-3: 115 MHz
			Spartan-3E: 90 MHz
			Spartan-3A/3AN/3A DSP:
			105 MHz
SysClk180_GBSL	Input	SysClk180: This clock is	Virtex-5: 275 MHz
V	(user interface)	the inverted equivalent of	Virtex-4: 190 MHz
		SysClk0_GBSLV. It is used
			Virtex-II Pro: 160 MHz
		to clock the internal
			Virtex-II: 160 MHz
		Source core logic.
			Spartan-3: 115 MHz
			Spartan-3E: 90 MHz
			Spartan-3A/3AN/3A DSP:
			105 MHz
TSClk_GBSLV	Input	TSClk: This clock is one-	Virtex-5: 69 MHz
	(user interface)	fourth the frequency of	Virtex-4: 47.5 MHz
		TDClk.
			Virtex-II Pro: 40 MHz
			Virtex-II: 40 MHz
			Spartan-3: 28.75 MHz
			Spartan-3E: 22.5 MHz
			Spartan-3A/3AN/3A DSP:
			105 MHz

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UG181 June 27, 2008