Source Core

R

The control signal TrainingRequest is used to request that training patterns be sent out of the Source SPI-4.2 interface. When this signal is asserted, data transmission is halted on the next burst boundary and training patterns are transmitted on the SPI-4.2 Interface. For more information on the behavior of TrainingRequest, see “Transmitting Training Patterns”.

The control signal IdleRequest signals that idle control words are to be sent on the SPI-

4.2bus. This request overrides payload data transfers, but not training sequence requests. When this signal is asserted, the data transmission is halted on the next burst boundary and idle cycles are transmitted on the SPI-4.2 Interface. Idle cycles continue to be transmitted until the signal is deasserted. For more information, see “Transmitting Idle Cycles”.

The control signal SrcTriStateEn allows you to set the IOB drivers to high impedance for Source core output signals TDClk, TDat[15:0], and TCtl. The Source core has the default setting for this signal as outputs not to be tri-stated (SrcTriStateEn=0).

The control signal SrcOofOverride removes the requirement that the Source core must receive consecutive valid DIP2 values on TStat. This signal forces the Source core to go in- frame, and begin transmitting data on the SPI-4.2 interface. This signal is intended for system testing and debugging.

The control signals SrcFifoReset_n and Reset_n provide reset capability to you:

•SrcFifoReset_n is used to clear the FIFO (and the associated data path logic) while remaining in-frame. When SrcFifoReset_n is deasserted, the Source core will send idle cycles until you write data into the FIFO.

•Reset_n is used to restart the entire Source core, and causes the interface to go out- of-frame. When Reset_n is deasserted, the Source core will initiate the synchronization startup sequence.

Source FIFO Interface Signals

The Source FIFO Interface signals allow you to write data to the FIFO for transmission to the SPI-4.2 Interface. The description of each signal is summarized in Table 2-12. The Source FIFO Interface signals are synchronous to SrcFFClk, and the effective FIFO depth is 510 words. A FIFO word is 1/2 credit wide for a 64-bit interface, and 1/4 credit wide for a 32-bit interface.

The SPI-4.2 Source core offers 64- and 32-bit FIFO Interface options for writing data into the FIFO. Waveforms illustrating handshaking and FIFO status signals are shown in Figure 4-24, Figure 4-25, and Figure 4-26. The Source core also supports insertion of DIP-4 errors on a per-packet basis for system diagnostics. For more information, see “Insertion of DIP-4 Errors,” page 85.

Source FIFO Almost Full

Figure 4-24shows the Almost Full response of the Source FIFO. The behavior of the Source Almost Full flag (SrcAlmostFull_n) is dependent on the static configuration signals SrcAFThresAssert and SrcAFThresNegate. When the SrcAlmostFull_n flag is asserted, SrcAFThresAssert specifies the number of available empty FIFO locations. For a 64-bit user interface, each FIFO location can contain up to 1/2 credit (8 bytes) worth of data from a single packet. For a 32-bit user interface, each FIFO location can contain up to 1/4 credit (4 bytes) worth of data from a single packet. SrcAFThresNegate specifies when the SrcAlmostFull_n flag is deasserted.

SPI-4.2 Lite v4.3 User Guide

www.xilinx.com

83

UG181 June 27, 2008

Page 82 Page 84
Page 83
Image 83
Xilinx UG181 manual Source Fifo Interface Signals, Source Fifo Almost Full
Page 82 Page 84

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
Top Page Image Contents