Xilinx UG181 Initializing the SPI-4.2 Lite Core, Keep it Registered, Use Supported Design Flows

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Chapter 4: Designing with the Core

Keep it Registered

The best method to simplify timing and increase system performance in an FPGA design is to keep everything registered. That is, all inputs and outputs from the user application should come from, or connect to, a flip-flop. While registering signals may not be possible for all paths, it simplifies timing analysis and helps you achieve timing closure.

Recognize Timing Critical Signals

Watch the timing and loading on the signals listed below. Some of these signals are part of the critical timing path. The following list of signals are timing critical and may require special attention when used in the user application:

•SnkFFRdEn_n

•SrcFFWrEn_n

Use Supported Design Flows

The SPI-4.2 Lite core has been tested with a variety of design flows. While other design tools can be used to simulate and synthesize your design with the core, their functionality cannot be guaranteed. See Chapter 7, “Simulating and Implementing the Core” for information about supported design tools.

Make Only Allowed Modifications

All modifications to the SPI-4.2 Lite core must be made using the Xilinx CORE Generator. Do not make other modifications as they may have adverse effects on system timing and SPI-4.2 protocol compliance.

Initializing the SPI-4.2 Lite Core

The SPI-4.2 Lite Sink and Source cores require initialization before receiving and transmitting data. The initialization steps are:

•Reset core

To reset the cores, the signal Reset_n must be asserted. The reset signal for each core must remain asserted until the clocks are ready for use.

•Reset DCMs

This step is only applicable if TDClk or RDClk is distributed using global clocking. The DCMs are only used when the global clocking option is selected. If regional clocking is selected for all clocks, this step can be skipped. If one or more DCMs are used, you must reset each DCM in the core while the core is in reset. Reset the DCM by asserting the DCM reset signal (ex: DCMReset_RDClk). Once the DCM reset is asserted, wait for the assertion of the DCM locked signal (ex: Locked_RDClk). When the locked signal is asserted, the clock is ready for use.

See “Sink Clocking Options,” page 111 and “Source Clocking Options,” page 115 for more information on the regional and global clocking options

•Deassert core reset

Once all the clocks are ready for use, the SnkClksRdy and SrcClksRdy signals will assert. The Reset_n signal can be deasserted only when these signals are asserted.

52	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008