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Logic Analyzer Concepts
The Trigger Sequence
Timing analyzer
When you configure a timing analyzer, the trigger sequence follows the
general outlines given previously. The trigger sequence of the timing
analyzer differs from the state analyzer in the following ways:
•There are 10 levels available to build a trigger.
•The trigger term is always the last step.
•The analyzer cannot use pattern terms h and j.
•The timing analyzer has two additional resources, Edge1 and Edge2.
•Edge1 and Edge2 recognize occurrences of a glitch, rising e dge, falling
edge, either edge, or no edge on a b it or ORed set of bits.
State analyzer
When you configure a state analyzer, the trigger sequence follows the
general outlines given previously. The trigger sequence of the state
analyzer differs from the timing analyzer in the following ways:
•There are 12 levels available to build a trigger.
•The trigger term is never the last step.
•The state analyzer cannot use Edge1 and Edge2.
•The state analyzer can use pattern terms h and j.