444
Specifications
General Information
Logic levels TTL, 3-state, TTL/3.3v,
3-state TTL/CMOS, ECL terminated,
ECL Unterminated, and differential
ECL (without POD)
Data inputs 3-bit pattern - level sensing (clock pod)
Clock outputs Synchronized to output data
Clock input DC to 200 MHz
Internal clock period Programmable from 5 ns to 250 us
in a 1, 2, 2.5, 4, 5, 8 sequence
External clock period (user supplied) DC to 200 MHz
External duty cycle 2 ns minimum high time
Maximum number of "IF condition" 1
blocks at 50 MHz
Maximum number for different Functions 100
Maximum number of lines in a Function 1024
Maximum number of Function invocations 1000
Maximum number of repeat loop invocations 1000
Maximum number of Wait event patterns 4