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Logic Analyzer Concepts
The Analyzer Hardware
The output of the clock select multiplexer is also distributed to an
external clock out circuit. The clock signal is routed to a bank of
external clock delays, and then to an external clock delay select
multiplexer. The output of this multiplexer, which represents the
desired clock delay, is directed to the external clock out pin on the
clock pod. Consequently, either the internal clock or external clock is
redirected to the clock out pin on the clock pod with a user-selected
clock delay.
CPU Interface
The CPU interface is a single programmable-logic device which
interprets the 1670EP Logic Analysis System backplane logic and
translates the logic into signals to drive and program the pattern
generator module.
Pod
The Clock or Data Pod converts the differential output ECL signal to
the logic levels of interest. Because the output of the pattern generator
module cannot directly drive ECL circuitry, the Clock and Data Pod is
required to interface the pattern generator with the target system.