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Logic Analyzer Concepts
The Analyzer Hardware
Attenuator/Preamp theory of operation
The channel signals are conditioned by the attenuator/preamps, thick
film hybrids containing passive attenuators, impedance converters, and
a programmable amplifier. The channel sensitivity defaults to the
standard 1-2-4 sequence (other sensitivities can be set also). However,
the firmware uses passive attenuation of 1, 5, 25, and 125, with the
programmable preamp, to cover the entire sensitivity range.
The input has a selectable 1 MW input impedance with ac or dc
coupling or a 50W input impedance with dc coupling. Compensation for
the passive attenuators is laser-trimmed and is not adjustable. After the
passive attenuators, the signal is split into high-frequency and low-
frequency components. Low frequency components are amplified on
the main assembly, where they are combined with the offset voltage.
The ac coupling is implemented in the low frequency amplifier.
The high- and low-frequency components of the signal are recombined
and applied to the input FET of the preamp. The FET provides a high
input impedance for the preamp. The programmable preamp adjusts
the gain to suit the required sensitivity and provides the output signal
to the main assembly. The output signal is then sent to both the trigger
circuitry and ADC.
Oscilloscope acquisition
The acquisition circuitry provides the sampling, digitizing, and storing
of the signals from the channel attenuators. The channels are identical.
Trigger signals from each channel and the external triggers
synchronize acquisition through the time base circuitry. A 100MHz
oscillator and a time base provide system timing and sample clocking.
A voltage-controlled oscillator (VCO), frequency divider, and digital
phase detector provide the sample clock for higher sample rates. After
conditioning and sampling, the signals are digitized, then stored in a
hybrid IC containing a FISO (fast in, slow out) memory.