Using indirect addressing method, this test writes increment data into the MAC Hash Register table and reads back for verification. The memory read/write is done 100 times while incrementing test data.
•A2. Control register test
Each register specified in the configuration contents are defined as read only bit and read/write bit. The test writes zero and one into the test bits to ensure the read only bits are not changed and read/write bits are changed accordingly.
•A3. Interrupt test
This test verifies the interrupt functionality. It enables interrupt and then waits for the interrupt to occur. It waits for 500ms and reports an error if it could not generate interrupts.
•A4.
This test initiates Hardware
•A5. PCI Cfg register test
This test verifies the access integrity of the PCI config registers.
Group B: Memory tests
•B1. Scratch pad test
This tests the scratch pad SRAM on board. The following tests are performed:
o Address test: Writes each address with unique increment data. Reads back data to ensure data is correct. After filling the entire data with the unique data, the program reads back data again to ensure data stays the same.
o Walking one bit test: For each address, data one is written and read back for testing. Then the data is shifted left one bit, so the data becomes two and the same test is run again. It repeats for 32 times until the test bit is shifted out of test data. The same test is repeated for the entire test range.
o Pseudo random data test: A
•B2. BD SRAM test
This tests the BD SRAM by performing the tests as described in test B1. The Scratch pad test.
•B3. DMA SRAM test
This tests DMA SRAM by performing the tests described in test B1. The Scratch pad test.
•B4. MBUF SRAM test
This tests DMA SRAM by performing the tests described in test B1. The Scratch pad test.
•B5. MBUF SRAM via DMA test
Eight test pattern data are used in the test. They are described below. A 0x1000 sized data buffer is used for this test. Before each pattern test, the buffer is initialized and filled with the test pattern. It then, performs size 0x1000 transmit DMA from host buffer to adapter MBUF memory. It verifies the data integrity in MBUF against host memory and repeats the DMA for the entire MBUF buffer. Then it performs receive DMA from adapter to host. The
Test Pattern Description:
