"16 00's 16 FF's" Fill the entire host DMA buffer with 16 bytes of 00's and then 16 bytes of FF's.

"16 FF's 16 00's" Fill the entire host DMA buffer with 16 bytes of FF's and then 16 bytes of 00's.

"32 00's 32 FF's" Fill the entire host DMA buffer with 32 bytes of 00's and then 32 bytes of FF's.

"32 FF's 32 00's" Fill the entire host DMA buffer with 32 bytes of FF's and then 32 bytes of 00's.

"00000000's" Fill the entire host DMA buffer with all zeros.

"FFFFFFFF's" Fill the entire host DMA buffer with all FF's.

"AA55AA55's" Fill the entire host DMA buffer with data 0xAA55AA55.

"55AA55AA's" Fill the entire host DMA buffer with data 0x55AA55AA.

Group C: Miscellaneous tests

C1. NVRAM test

An increment test data is used in the EEPROM test. It fills the test data into the test range and reads it back to verify the content. After the test, it fills data with zeros to clear the memory.

C2. CPU test

This test opens the file cpu.bin. If the file exists and the content is good, it loads code to the Rx and Tx CPU and verifies CPU execution.

C3. DMA test

This tests both high and low priorities DMA. It moves data from host memory to adapter SRAM, verifies data, and then moves data back to the host memory again to verify data.

C4. MII test

This function is identical to A2. Control Register Test. Each Register specified in the configuration contents is defined as read only bit and read/write bit. The test writes zero and one into the test bits to ensure the read only bits are not changed and read/write bits are changed accordingly.

C5. VPD test

The content of VPD is saved first before performing the test. After it is saved, the test writes one of the five pattern test data, 0xff, 0xaa, 0x55, increment data, or decrement data, into VPD memory. By default, increment data pattern is used. It writes and reads back the data for the entire test range, and then it restores the original content.

C6. ASF test

The function of this test is as follows:

o Reset test. Sets the reset bit and polls for self-clearing. Verifies the reset value of the registers.

o Event Mapping Test. Sets SMB_ATTN bit by changing ASF_ATTN LOC bits. Verifies the mapping bits in TX_CPU or RX_CPU event bits.

o Counter Test. Clears WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits by setting those bits. Makes sure the bits are clear. Clears the Timestamp Counter. Writes a value 1 into each of the PL, PA, HB, WG, RT counters. Sets the TSC_EN bit. Polls each PA_TO bit and counts up to 50 times.

Checks if PL_TO gets set at the end of 50 times. Continues to count up to 200 times. Checks if all other TO bits are set and verifies the Timestamp Counter is incremented.

C7. Expansion ROM test

This tests the ability to enable/disable/access the expansion ROM on the device.

Group D: Driver associated tests

D1. Mac loopback test

Diagnostics 159