•Link Status Change Count
This counter indicates the number of times the link status has been changed.
•Rx CRC Error Count
This counter indicates the number of receive packets with CRC errors. Packets less than 64 bytes are not counted in this statistic.
•Alignment Errors
This counter holds the number of receive packets with alignment errors. In order for a packet to be counted, it must pass address filtering and must be 64 bytes or greater in length. If receives are not enabled, then this counter does not increment. This counter is valid only in MII mode during 10/100 Mbps operation.
•Rx Symbol Error Count
This counter indicates the number of symbol errors between reads. The count increases for every bad symbol received, whether or not a packet is currently being received and whether or not the link is up. This counter will increment along with the Rx Sequence Error Count when either the fiber cable is disconnected or the connector is not seated completely. Also, during driver load, this counter will increments minimally.
•Rx Error Count
This counter indicates the number of packets received in which I_RX_ER was asserted by the PHY. In order for a packet to be counted, it must pass address filtering and must be 64 bytes or greater (from <Destination Address> through <CRC>, inclusively) in length. If receives are not enabled, then this counter does not increment. In TBI mode, this counter increments on the reception of /V/ codes.
•Rx Missed Packets Count
This counter indicates the number of missed packets. Packets are missed when the hardware receive FIFO has insufficient space to store the incoming packet. This could be the result of having too few buffers allocated or because there is insufficient bandwidth on the IO bus. These packets are also be counted in the Total Packets Received counter as well as in Total Octets Received.
•Tx Single Collision Count
This counter indicates the number of times that a transmitted packet encountered a single collision. This counter increments only if the device is in
•Tx Excessive Collisions Count
This counter indicates when 16 or more collisions have occurred on a packet. This counter increments only if the device is in
•Tx Multiple Collision
This counter indicates the number of times that a transmitted packet encountered more than one collision but less than 16. This counter increments only if the device is in
•Tx Late Collisions Count
This counter indicates collisions that occur after 512 bit (64 byte) times. This counter increments only if the device is in
•Tx TOTAL Collision
This counter indicates the total number of collisions seen by the transmitter. This counter increments only if the device is in
•Tx DMA Underruns
