Paradyne 9126-II, CSU, DSU, 9128-II manual Idle

Models: CSU, DSU 9126 9126-II 9128-II

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4. Configuration Options

Table 4-12. Signaling and Trunk Conditioning Values (2 of 3)

Network Side

Meanings

DSX-1 Side

 

 

 

E&M-idle

The signaling bits transmitted to the cross-connected

E&M idle

 

T1 interface during a CGA represent the idle state for

 

 

an E&M interface (ABCD = 0000).

 

 

 

 

E&M-busy

The signaling bits transmitted to the cross-connected

E&M busy

 

T1 interface during a CGA represent the busy state

 

 

for an E&M interface (ABCD = 1111).

 

 

 

 

FXOg-idle

The signaling bits transmitted to the cross-connected

FXSg-idle

 

T1 interface during a CGA represent the idle state for

 

 

an FXO Ground-Start interface (ABCD = 1111).

 

 

 

 

FXOg-busy

The signaling bits transmitted to the cross-connected

FXSg-busy

 

T1 interface during a CGA represent the busy state

 

 

for an FXO Ground-Start interface (ABCD = 0101).

 

 

 

 

FXOl-idle

The signaling bits transmitted to the cross-connected

FXSl-idle

 

T1 interface during a CGA represent the idle state for

 

 

an FXO Loop-Start interface (ABCD = 0101).

 

 

 

 

FXOl-busy

The signaling bits transmitted to the cross-connected

FXSl-busy

 

T1 interface during a CGA represent the busy state

 

 

for an FXO Loop-Start interface (ABCD = 0101).

 

 

 

 

FXSg-idle

The signaling bits transmitted to the cross-connected

FXOg-idle

 

T1 interface during a CGA represent the idle state for

 

 

an FXS Ground-Start interface (ABCD = 0101).

 

 

 

 

FXSg-busy

The signaling bits transmitted to the cross-connected

FXOg-busy

 

T1 interface during a CGA represent the busy state

 

 

for an FXS Ground-Start interface (ABCD = 1111).

 

 

 

 

FXSl-idle

The signaling bits transmitted to the cross-connected

FXOl-idle

 

T1 interface during a CGA represent the idle state for

 

 

an FXS Loop-Start interface (ABCD = 0101).

 

 

 

 

FXSl-busy

The signaling bits transmitted to the cross-connected

FXOl-busy

 

T1 interface during a CGA represent the busy state

 

 

for an FXS Loop-Start interface (ABCD = 1111).

 

 

 

 

FXOD-idle

The signaling bits transmitted to the cross-connected

FXSD-idle

 

T1 interface during a CGA represent the idle state for

 

 

an FXODN interface (ABCD = 0000).

 

 

 

 

FXOD-busy

The signaling bits transmitted to the cross-connected

FXSD-busy

 

T1 interface during a CGA represent the busy state

 

 

for an FXODN interface (ABCD = 1111).

 

 

 

 

FXSD-idle

The signaling bits transmitted to the cross-connected

FXOD-idle

 

T1 interface during a CGA represent the idle state for

 

 

an FXSDN interface (ABCD = 0000).

 

 

 

 

FXSD-busy

The signaling bits transmitted to the cross-connected

FXOD-busy

 

T1 interface during a CGA represent the busy state

 

 

for an FXSDN interface (ABCD = 1111).

 

 

 

 

9128-A2-GB20-80

September 2002

4-57

Page 101
Image 101
Paradyne 9126-II, CSU, DSU, 9128-II manual Idle