Paradyne 9128-II, CSU, DSU, 9126-II manual PLAR3idle

4. Configuration Options

Table 4-12. Signaling and Trunk Conditioning Values (3 of 3)

Network Side	Meanings	DSX-1 Side
PLAR3idle	The signaling bits transmitted to the cross-connected	PLAR3idle
	T1 interface during a CGA represent the idle state for
	a PLAR D3 interface (ABCD = 0000).
PLAR3busy	The signaling bits transmitted to the cross-connected	PLAR3busy
	T1 interface during a CGA represent the busy state
	for an PLAR D3 interface (ABCD = 1111).
PLAR4idle	The signaling bits transmitted to the cross-connected	PLAR4idle
	T1 interface during a CGA represent the idle state for
	a PLAR D4 interface (ABCD = 1111).
PLAR4busy	The signaling bits transmitted to the cross-connected	PLAR4busy
	T1 interface during a CGA represent the busy state
	for an PLAR D4 interface (ABCD = 0000).
DPO-idle	The signaling bits transmitted to the cross-connected	DPT-idle
	T1 interface during a CGA represent the idle state for
	a DPO interface (ABCD = 0000).
DPO-busy	The signaling bits transmitted to the cross-connected	DPT-busy
	T1 interface during a CGA represent the busy state
	for a DPO interface (ABCD = 1111).
DPT-idle	The signaling bits transmitted to the cross-connected	DPO-idle
	T1 interface during a CGA represent the idle state for
	a DPT interface (ABCD = 0000).
DPT-busy	The signaling bits transmitted to the cross-connected	DPO-busy
	T1 interface during a CGA represent the busy state
	for a DPT interface (ABCD = 1111).
USER-xxxx	The signaling bits transmitted to the cross-connected	USER-xxxx*
	T1 interface during a CGA represent a user-defined
	pattern of ABCD = xxxx.

* xxxx is the same value on both the Network and the DSX-1 sides.

4-58 September 2002 9128-A2-GB20-80