TMP92CZ26A

92CZ26A-165

Port T register

7 6 5 4 3 2 1 0

bit Symbol PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0
Read/Write R/W
After reset Data from external port (Output latch register is cleared to “0”)
Port T control register

7 6 5 4 3 2 1 0

bit Symbol PT7C PT6C PT5C PT4C PT3C PT2C PT1C PT0C
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function 0: Input 1: Output
Port T function register

7 6 5 4 3 2 1 0

bit Symbol PT7F PT6F PT5F PT4F PT3F PT2F PT1F PT0F
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function 0: Port 1: Data bus for LCDC (LD15 to LD8)
Port T drive register

7 6 5 4 3 2 1 0

bit Symbol PT7D PT6D PT5D PT4D PT3D PT2D PT1D PT0D
Read/Write R/W
After reset 1 1 1 1 1 1 1 1
Function Input/Output buffer drive register for standby mode
Note1: Read-Modify-Write is prohibited for the registers PTCR, PTFC.
Note2: When PT is used as LD15 to LD8, set applicable PTnC to”1”.

Figure 3.7.53 Register for Port T

PT
(00A0H)
PTFC
(00A3H)
PTCR
(00A2H)
PTDR
(009BH)