Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-735

TMP92CZ26A
92CZ26A-735
(15) 16-bit timer (2/2)
Symbol Name Address 7 6 5 4 3 2 1 0
TB1RDE − I2TB1 TB1PRUN TB1RUN
R/W R/W R/W R/W R/W
0 0 0 0 0
TMRB0
prescaler
Up
counter
(UC12)
TB1RUN TMRB1
RUN
register 1190H Double
buffer
0: disable
1: enable
Always
write “0”. IDLE2
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
− − TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0
R/W W* R/W
0 0 1 0 0 0 0 0
TB1MOD TMRB1
MODE
register
1192H
(Prohibit
RMW)
Always write “00”. Software
capture
control
0: Execute
1:
Undefined
Capture timing
00: Disable
INT7 occurs at rising
edge
01: TB1IN0 ↑
INT7 occurs at rising
edge
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at falling
edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
Control
Up
counter
0:Clear
Disable
1:Clear
Enable
TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
− − TB1CT1 TB1C0T1 TB1E1T1 TB1E0T1 TB1FF0C1 TB1FF0C0
W R/W W*
1 1 0 0 0 0 1 1
TB1FF0 inversion trigger
0: Disable trigger
1: Enable trigger
TB1FFCR
TMRB1
Flip-Flop
control
register
1193H
(Prohibit
RMW)
Always write “11”.
*Always read as “11”.
When
capture
UC12 to
TB1CP1H/L
When
capture
UC12 to
TB0CP0H/L
When UC12
matches
with
TB1RG1H/L
When UC12
matches
with
TB1RG0H/L
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read as “11”.
−
W
TB1RG0L 16 bit timer register 0
low
1198H
(Prohibit
RMW) 0
−
W
TB1RG0H 16 bit timer register 0
high
1199H
(Prohibit
RMW) 0
−
W
TB1RG1L 16 bit timer
register low
119AH
(Prohibit
RMW) 0
−
W
TB1RG1H 16 bit timer register 1
high
119BH
(Prohibit
RMW) 0
−
R
TB1CP0L Capture register 0
low 119CH
Undefined
−
R
TB1CP0H Capture register 0
high 119DH
Undefined
−
R
TB1CP1L Capture register 1
low 119EH
Undefined
−
R
TB1CP1H Capture register 1
high 119FH
Undefined