TMP92CZ26A

92CZ26A-245

Reed-Solomon ECC
• The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be
used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated
several times to cover the entire page.
• Basically no calculation is needed for error correction. If error detection is performed properly , the NDFC
only needs to refer to the error address and error bit. However , it may be necessary to convert the error
address, as explained below.
1) If the error address indicated by the NDRSCAn register is in the range of 000H to
007H, this error exists in the ECC area and no c orrection is needed in this case.
(It is not able to correct the error in the ECC area. However, if the error exists in the
ECC area, on ly 4symbol (include the er ror in the ECC area) c an correct the error to this
LSI. Please be careful.)
2) If the error address indicated by the NDRSCAn register is in the range of 008H to
20DH, the actual error address is obtained by subtracting this a ddress from 20 DH.
(If the valid data is processed as 512 byte, the actual error address is obtained by
subtracting this address from 207H when the error address in the range of 008H to
207H.)
Example 1:
NDRSCAn = 005H, NDRSCDn = 04H = 00000100B
As the error address (005H) is in the range of 000H to 007H, no correction is needed.
(Although an error exists in bit 2, no correction is needed.)
Example 2:
NDRSCAn = 083H, NDRSCDn = 81H = 10000001B
The actual error address is obtained by subtracting 083H from 20DH. Thus, the error correction process inverts
the data in bits 7 and 0 at address 18AH.
(If the valid data is 512 byte, the actual error address is obtained by subtracting 083H from 207H. Thus, the error
correction process inverts the data in bits 7 and 0 at address 184H.)
Note: If the error address (after conver t ed) is in the rang e of 00 0H to 007 H, it indicates th at an e rro r bit exists in
redundant area (ECC). In this case, no error correction is needed. If the number of error bits is not more
than 4 symbols, Reed-Solomon codes calculate each error bit precisely even if it is the redundant area
(ECC).