TMP92CZ26A

92CZ26A-540

LCD Control 0 Register
7 6 5 4 3 2 1 0
bit Symbol PIPE ALL0 FRMON – DLS LCP0OC START
Read/Write R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0
Function
PIP
function
0:Disable
1:Enable
Segment
data
setting
0: Normal
1: Always
output “0”
Frame
divide
setting
0: Disable
1: Enable
Always
write “0”
LFR signal
LCP0/line
selection
0:Line
1:LCP0
LCP0 (Note)
0: Al ways
output
1: At valid
d
ata onl
y
LLOAD
width
0: At setting
in register
1: At valid
data only
LCDC
operation
0: Stop
1: Start
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
Divide FRM 0 Register
7 6 5 4 3 2 1 0
bit Symbol FMP3 FMP2 FMP1 FMP0 FML3 FML2 FML1 FML0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function LCP0 DVM (bits 3-0) (M) LHSYNC DVM (bits 3-0) (N)
7 6 5 4 3 2 1 0
bit Symbol FMP7 FMP6 FMP5 FMP4 FML7 FML6 FML5 FML4
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function LCP0 DVM (bits7-4) (M) LHSYNC DVM (bits 7-4) (N)

LCDDVM0
(0283H)
LCDDVM1
(0284H)
LCDCTL0
(0285H)