Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-541

TMP92CZ26A
92CZ26A-541
6. LD Bus
The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to
LD0). The output format can be selected according to the input method of the LCD
driver to be used.
The LCDC reads data of the size corresponding to the specified LCD size from the
display RAM and transfers it to the external LCD driver via the data bus pin dedicated
to the LCD. Thus, the LCDC automatically issues a bus request to the CPU (to stop
CPU operation) when it needs to read data from the display RAM. The bus occupancy
rate of the LCDC varies depend ing on the d isp lay mode and the speed at which d a ta is
read from the display RAM.
Display RAM Bus Width Valid Data Read Time
(fSYS clocks/bytes)
Valid Data Read Time
tLRD(ns/bytes)
at fSYS = 60 MHz
External SRAM 16-bit (2 + number of waits) / 2 16.6
Internal RAM 32-bit **1/4 **4.16
External SDRAM 16-bit *1/2 *8.33
Note: When SDRAM is used, ad ditional 9 clocks are nee ded as ove rhead time fo r reading each common (line)
data. When internal RAM is used, additional 1 clock is needed as overhead time for reading each common
(line) data. Additional 1 clock of overhead time is also needed when a change of blocks occur in the
internal RAM even if the common (line) remains the same.
The time the CPU stops operating while data for one common (line) is being
transferred is defined as tSTOP, which is represented by the following equation:
t
STOP = (SegNum × K / 8) × tLRD
SegNum : Number of display segments
K : Number of bits needed for displaying one pixel
Monochrome display K=1
4-grayscale display K=2
16-grayscale display K=4
256-color display K=8
4096-color display K=12
65536-color display K=16
262144-/16777216-color display K=24
Note: When SDRAM is used, overhead time is added as follows:
tSTOP [S] = ( SegNum × K / 8 ) × tLRD + ((1 / fSYS ) × 8 )
The bus occupancy rate indicates the proportion of the one common (line) update time tLP occupied by tSTOP and
is calculated by the following equation:
CPU bus occupancy rate = tSTOP [s] / LHSYNC [s: period]