Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-650, 4.3.2 Page ROM Read Cycle

TMP92CZ26A
92CZ26A-650
4.3.2 Page ROM Read Cycle
(1) 3-2-2-2 mode
Variable
Parameter Symbol Min Max 80 MHz 60 MHz Unit
1 System clock period ( = T) tCYC 12.5 266.6 12.5 16.6
2 A0, A1 → D0 ~ D15 input tAD2 2.0T − 18 7 15.2
3 A2 ~ A23 → D0 ~ D15 input tAD3 3.0T
− 18 19.5 31.8
4 RD falling → D0 ~ D15 input tRD3 2.5T − 18 13 24
5 A0 ~ A23 Invalid → D0 ~ D15 hold tHA 0 0 0
6 RD rising → D0 ~ D15 hold tHR 0 0 0
ns
AC measuring condition
Note: The (a), (b) and (c) of “Symbol” in ab ove table depend on the fall ing timing of RD pin. The falling timing of
RD pin is set by MEMCR0<RDTMG1:0> in memory controller. If MEMCR0<RDTMG1:0> is set to “00”, it
correspond with (a) in above table, and “01” is (b), “10” is (c).
SDCLK
A2~A23
A0~A1
2CS
RD
D0~D15
+0
+
1
+
2+3
Data
input Data input Data input Data input
tAD3 tAD2 tAD2 tAD2 tH
A
tHR
tRD3 tH
A
tH
A
tH
A
tCYC