Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-193

TMP92CZ26A
92CZ26A-193
(6) Adjust Function for the timing of con trol signal
This function can change the timing of CSn ,CSZx ,CSXx ,R/W,RD ,WRxx ,SRWR andSRxxB
signals and adjust the timing accord ing to the set-up/hold time of the memories.
As for the CSn ,CSZx ,CSXx ,R/Wand WRxx ,SRWR ,SRxxB (at write cycle), it can be changed
for only 1 CS area. While for RD and SRxxB (at read cycle), it can be changed for all CS
areas. As for CS area and EX area which is not set this function, it operates with base bus
timing (Refer to (7)).
This can not be used together with BnCSH< BnREC> function.
For control signal of SDRAM, it can be adjusted in SDRAM controller.
CSTMGCR<TxxSEL1:0>, WRTMGCR<TxxSEL1:0>
00 Change the timing of CS0 area
01 Change the timing of CS1 area
10 Change the timing of CS2 area
11 Change the timing of CS3 area
CSTMGCR<TAC1:0>
00 TAC = 0 × fSYS (Default)
01 TAC = 1 × fSYS
10 TAC = 2 × fSYS
11 (Reserved)
TAC:The delay from (A23-0) to (CSn, CSZx, CSXx, R/W).
WRTMGCR<TCWS/H1:0>
00 TCWS/H = 0.5 × fSYS (Default)
01 TCWS/H = 1.5 × fSYS
10 TCWS/H = 2.5 × fSYS
11 TCWS/H = 3.5 × fSYS
TCWS:The delay from (CSn) to (WRxx,SRWR,SRxxB).
TCWH:The delay from (WRxx,SRWR,SRxxB) to (CSn).
RDTMGCR0/1<BnTCRH1:0>
00 TCRH = 0 × fSYS (Default)
01 TCRH = 1 × fSYS
10 TCRH = 2 × fSYS
11 TCRH = 3 × fSYS
TCRH:The delay from (RD,SRxxB) to (CSn).