Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-329

TMP92CZ26A
92CZ26A-329
7 6 5 4 3 2 1 0
bit Symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC
Read/Write R R/W R (cleared to 0 when read) R/W
After Reset Undefined 0 0 0 0 0 0 0
Function
Received
dat a bit 8
Parity
0: od d
1: ev en
Parity
addition
0: disable
1: en ab le Overrun Parity Framing
0: SCLK0
1: SCLK0
0: baud rate
generator
1: SCLK0
pin input
SC0CR
(1201H)
I/O interface input clock selection
Fr ami ng E rror f l ag
Parit y Error flag
Ov errun Error flag
0Tr ans mi ts and r eceivers
dat a on risi n g ed ge of SCLK0.
1Tr ans mi ts and r eceivers
data on falling edge SCLK0.
Edge selection for SCLK pin (Input / Output Mode)
0 Disabled
1 Enabled
P arity addition enables
E ven p arit y ad dit i on/c h ec k
1: error
0 Baud rate gen erat or
1 SCLK0 pin input
Cleared to 0
when read
0 Odd parity
1 Even parity
Rec eived data 8
Prohibit
to Read
modify
Write
Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing
instruction.
Figure 3.14.7 Serial Control Register (ch annel 0, SC0CR)