TMP92CZ26A

92CZ26A-481

(h) <SWRST>
This bit is for Software reset of transmit/receive FIFO pointer. Write SPICT<TXE> to
“0” at <XEN>="1", and stop transmitting. After that, by writing <SWRST> to “1”, the
read/write pointer of tr ansmit/receive FIFO are initialized.
When writing SPICT<TXE> to “0”, stops transmission after the UNIT data in
transmitting is transmitted. Write <SWRST> to“1”, the data in the transmit FIFO
becomes to invalid.
The data in th e transmit shift r egister is cleare d simultane ously. Therefore, the data is
not output if transmit is restarted after executed software reset.
Please do not write <SWRST> to “1” during transmission. In case of receiving, the
received data in the receive FIFO buffer becomes invalid. However, the UNIT data in
receiving is loaded to receive FIFO as valid data.
In case of sequential receive, rec ei ving operates sequentially e ven if the data of receive
buffer becomes invalid. Therefore, stops receive operation by writing
SPICT<RXE>=“0”after finishing to receive all the data in receiving. And all the receive
operation is stopped by writing <SWRST>=“1”after checking no UNIT data in receiving
(namely after REND interrupt or the time to receive 1UNIT).
During receiving, do not write <SWRST>=“1”.
Software reset can be executed by 1 shot operation; writing <SWRST>=“1” (needless to
write <SWRST>=“0”). Writing <XEN>=“1”and <SWRST>=“1”simultaneously is permitt e d.
(i) <XEN>
Enable/disable control of root clock this SPI controller.
(j) <CLKSEL2:0>
Select baud rate. Baud rate is created from fSYS and settings are in under table.
Please change the setting when transmitti ng/receiving are not in operation.
Note: When setting the baud rates, select less than 20Mbps according to the operation speed of CPU (fSYS).
Table 3.17.1 Example of Baud Rate
Baud Rate [Mbps]
<CLKSEL2:0> fSYS =60MHz fSYS =80MHz
fSYS/2 − −
fSYS /3 20 −
fSYS /4 15 20
fSYS /8 7.5 10
fSYS /16 3.75 5
fSYS /64 0.9375 1.25
fSYS /256 0.234375 0.3125