Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-403

TMP92CZ26A
92CZ26A-403
3.16.3.22 INT_Control Register
INT_STASN interrupt is disabled and enabled by value that is written to this
register.
This is initialized to disable by external reset. When setup packet is received, it
becomes to disable.
7 6 5 4 3 2 1 0
bit Symbol Status_nak
Read/Write R/W
After reset 0
In control read transfer, if host terminate dataphase in small data length (smaller
than data length that is specified to wLength by host), device side and stage
management cannot be synchronized. Therefore, INT_STASN interrupt inform that
shift to status stage.
If this interrupt don’t need, it can set t o disab le bec ause of this interru pt is a sserted
every status stage.
STATUS_NAK (Bit0)
0: INT_STATSN interrupt disable
1: INT_STATSN interrupt enable
3.16.3.23 USB STATE Register
This register shows devic e state of present for conn ecti on with USB host.
7 6 5 4 3 2 1 0
bit Symbol Configured Addressed Default
Read/Write R/W R R
After reset 0 0 1
Inside UDC, answer for each Device Request is managed by referring this bits
(Configured, Addressed and Default). If transaction for SET_CONFIG request is
executed by using s oftwa re, write pr esent stat e to this re gister. If host appointcon fig0,
this becomes Unconfigured. And returning to Addressed state is needed. Therefore, if
host appoint config0, write bit2 to “0”.
When Configured bit (Bit2) is written “0”, Addressed bit (bit 1) is set automatically
by hardware. When host appoint config value that supported by device, device must
execute mode setting of each endpoint by using value that is appointed by
endpoint-descriptor in the config-descriptor. After finish mode setting, set Configured
bit (Bit2) to “1” before access EOP register. When this bit is set to “1”, Addressed bit
(Bit1) is set to “0” automatically.
Bit2 to bit0
000: Default
010: Addressed
100: Configured
INT_Control
(07D6H)
USB STATE
(07CEH)