Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-237, 3.10.4 Considerations for Using the SDRAMC

TMP92CZ26A
92CZ26A-237
3.10.4 Considerations for Using the SDRAMC
This section describes the points that must be taken into account when using the SDRAMC.
Please carefull y read the following t o ensure proper use of the SD RAMC.
1) WAIT access
When SDRAM is used, the following restriction applies to memory access to other than
the SDRAM.
In the external WAIT pin input setting of the memory controller, the maximum external
WAIT period that can be set is limit ed to “Auto Refresh interval × 8190”.
2) Execution of the Self Refresh En try, In itialization S equence, or Pr echarge All command
before the HALT instruction
Execution of the commands issued by the SDRAMC (Self Refresh Entry, Initialization
Sequence, Precharge All) requires several states after the SDCMM register is set.
Therefore, to execut e the HAL T instruction after one of thes e commands, be sure to insert
at least 10 bytes of NOP or other instructions.
3) Auto Refresh interval setting
When SDRAM is used, the system clock frequency must be set to satisfy the minimum
operation frequency and minimum Auto Refresh interval of the SDRAM to be used.
In a system in which SDRAM is used and the clock is geared up and down, the Auto
Refresh interval mu st be set carefully.
Before changing the Auto Refresh interval, ensure that SDRCR<SRC> is set to “0” to
disable the Auto Refresh function.
4) Changing SFR settings
Before changing the settings of the SDACR<SPRE> and SDCISR registers, ensure that
the SDRAMC is disabled (SDACR<SMAC> =“0”).
5) Disabling the SDRAMC
Set the following procedure, when disable the SDRAMC.
LD (SDCMM),0x02 ; Issue to All Bank Precharge
LOOP: LD A,(SDCMM) ; Read SDCMM
CP A,0x00 ; Palling it until the All Bank Precharge command is
finished
JP NZ,LOOP ;
LD (SDACR),0x00 ; Stop the SDRAM controller