TMP92CZ26A
92CZ26A-417
3.16.5.2 Printer Class Request
UDC does not support “Autom atic answer” of print er class re quest.
Transaction for Class request is the same as vendor request; answering to
INT_SETUP interrupt.
3.16.5.3 Vendor request (Cl ass request)
UDC doesn’t support “Automatic answer” of Vendor request.
According to INT_SETUP interrupt, access register that device request is stored,
and discern receiv ing re qu est. If th is re quest is v end or requ est, c ontrol UD C from
external, and ex ecute transaction for Vendor requ est.
Below is explanation for case of data phase is transmitting (Control read), and
case of data phase is receiving ( C ontrol write).
(a) Control Read r equest
bmRequestType bRequest wValue wIndex wLength Data
110000xxB Vender peculiar Vender peculiar Vender peculiar Vender peculiar
(Expire 0) Vendor data
When INT_SETUP is received, judge contents of receiving request by
bmRequestType, bRequest, wValue, wIndex and wLength registers. And execute
transaction for each request. As application, access Setup_Received register after
request was judged. And it must inform that INT_SETUP interrupt was
recognized to UDC.
After transmitting data pr epared in applic ation, access DA TASET register, and
confirm EP0_DSET_A bit is “0”. After confirming, write data FIFO of endpoint 0 .
If transmitting data more than payload, write data after it confirmed whether a
bit of EP0_DSET_A in DATASET register is “0”. (INT_ENDPOINT0 interrupt is
can be used.) If writing all data finished, write “0” to EP0 bit of EOP register.
When UDC receive it, status stage f in ish autom atically.
And when UDC finish status stage normally, INT_STATUS interrupt is
asserted. If finishing status stage normally is recognized to external application,
manage this stage by using this interrupt signal. If status stage cannot be
finished normally and during status stage, maybe new SETUP token is received.
In this case, when INT_SETUP interrupt signal is asserted, “1” is set to
STAGE_ERROR bit of EP0_STATUS register. And it informs it to external that
status stage cannot be finished normally.
And maybe dataphase finish in data number that is short than value showed
to wLength by protocol of control read transfer type in USB. If application
program is configured by using only wLength value, transaction for it cannot be
when host shift to status stage wit hout arriving at expecting data number. At this
point, shifting to status stage can be confirmed by using INT_STATUSNAK
interrupt signal. (However, releasing mask of STATUS_NAK bit by using
interrupt control register is needed.) In Vendor Request, this problem will not
generate because of receiving buffer size is set to host controller by driver,
actually.
Note: In every host, data (data that is transmitted from device by payload of 8 bytes) may be
recognized to short packet until confirming payload size of device side. And it may become to above
case on the exterior. Therefore, if controlling standard request by using software, be careful.)