Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-505, 3.18.4 Detailed Description of Operation

TMP92CZ26A
92CZ26A-505
3.18.4 Detailed Description of Operation
(1) Connection example
Figure 3.18.5 shows an example of connections between the TMP92CZ26A and an
external LSI (DA converter) using channel 0.
Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor
as necessary.
Figure 3.18.5 Connection Example between the TMP92CZ26A and an External LSI
(2) Operation pr oce d ure
The I2S unit incorporates a 128-byte FIFO buffer that is divided into two 64-byte units.
Whenever each 64-byte buffer space becomes empty, an INTI2Sn interrupt is generated.
The next data to be transmitted should be written to the FIFO in the interrupt routine.
Example settings an d timing diagram are shown below.
(Example settings) I2S0WS = 8 KHz, I2SnCKO = 400 kHz, data transmission on the rising edge (at fSYS = 50 MH z)
(Main routine)
7 6 5 4 3 2 1 0
INTEI2S01
X − − − X 0 0 1 Set interrupt level.
PFCR X X − − −
− − −
PFFC − X − − −
111
Set pins: PF0 (I2S0CKO), PF1 (I2S0DO), PF2 (I2S0WS)
1 0 0 1 0 1 1 0 Divider value N=150 I2S0SC
X X 1 1 0 0 1 0 Divider value K=50
0 0 X 0 1 0 0 1 Set transmit mode (I2S mode, MSB-first, 16-bit). I2S0CTL
0 X X X X 0 0 0 Falling edge, WS=0 Left, clock stop.
* * * * * * * * Write left and right data to FIFO (4 bytes x 32 = 128 bytes).
* * * * * * * *
* * * * * * * *
I2S0BUF
* * * * * * * *
I2S0CTL
1 0 X 0 1 0 0 1 Start transmission.
0 X X X X 0 0 0
(INTI2S Interrupt Routine)
* * * * * * * * Write left and right data to FIFO (4 bytes x 16 = 64 bytes).
* * * * * * * *
* * * * * * * *
I2S0BUF
* * * * * * * *
X: Don't care, −: No change
(Transmit)
PF2/I2S0WS
PF0/I2SCKO
PF1/I2SDO
(Receive)
WS
CK
DATA
TMP92CZ26A
Example: DA converter