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Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-455

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TMP92CZ26A

92CZ26A-455

(b) Condition change

Initialization transaction

Turn on power supply

Waiting USB

interrupt condition

Request

transaction

condition

Receive USB token

Transmit Request

error/

Transaction error/

Transmit STALL

Normal finish/No transaction

Contents

Main Data Book 32bit Micro controller TLCS-900/H1 series TMP92CZ26AXBG Rev0.2 09/Dec./2005 TENTATIVE Table of Contents TLCS-900/H1 Devices TMP92CZ26A Page TMP92CZ26A 92CZ26A-1 CMOS 32-Bit Micro controllers TMP92CZ26AXBG 1. Outline and Features TMP92CZ26A 92CZ26A-2 TMP92CZ26A 92CZ26A-3 TMP92CZ26A 92CZ26A-4 TMP92CZ26A 92CZ26A-5 TMP92CZ26A 92CZ26A-6 2. Pin Assignment and Pin Functions 2.1 Pin Assignment Diagram (Top View) TMP92CZ26A TMP92CZ26A 92CZ26A-7 Table 2.1.1 Pin number and the name TMP92CZ26A 2.2 Pin names and Functions TMP92CZ26A 92CZ26A-9 T able 2.2.1 Pin names and functions (2/6) TMP92CZ26A 92CZ26A-10 Table 2.2.1 Pin names and functions (3/6) TMP92CZ26A 92CZ26A-11 Table 2.2.1 Pin names and functions (4/6) TMP92CZ26A 92CZ26A-12 Table 2.2.1 Pin names and functions (5/6) TMP92CZ26A 92CZ26A-13 Table 2.2.1 Pin names and functions (6/6) operational voltage 3. Operation This section describes the basic components, functions and operation of the T MP92CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high -speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline TMP92CZ26A 92CZ26A-15 3.1.2 Reset Operation TMP92CZ26A 92CZ26A-16 TMP92CZ26A 92CZ26A-17 TMP92CZ26A 92CZ26A-18 3.1.3 Setting of AM0 and AM1 TMP92CZ26A 3.2 Memory Map 3.3 Clock Function and Standby Function TMP92CZ26A 92CZ26A-21 Figure 3.3.1 System clock block diagram TMP92CZ26A 92CZ26A-22 Figure 3.3.2 Block Diagram of System clock f TMP92CZ26A 92CZ26A-23 TMP92CZ26A 92CZ26A-24 3.3.2 SFR 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-25 7 6 5 4 3 2 1 0 Figure 3.3.4 SFR for system clock TMP92CZ26A 92CZ26A-26 TMP92CZ26A 92CZ26A-27 3.3.3 System clock controller TMP92CZ26A 92CZ26A-28 3.3.4 Clock doubler (PLL) TMP92CZ26A 92CZ26A-29 (Example-2) PLL0-stopping TMP92CZ26A 92CZ26A-30 TMP92CZ26A 92CZ26A-31 3.3.5 Noise reduction circuits TMP92CZ26A 92CZ26A-32 TMP92CZ26A 92CZ26A-33 TMP92CZ26A 92CZ26A-34 3.3.6 Standby controller TMP92CZ26A 92CZ26A-35 TMP92CZ26A 92CZ26A-36 (interrupt level) < (interrupt mask) Halt mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP TMP92CZ26A 92CZ26A-37 TMP92CZ26A 92CZ26A-38 TMP92CZ26A 92CZ26A-39 TMP92CZ26A 92CZ26A-40 Table 3.3.6 Input Buffer State Table Input Buffer State In HALT mode (IDLE2/1/STOP) When the CPU is operating <PxDR>=1 <PxDR>=0 TMP92CZ26A 92CZ26A-41 Table 3.3.7 Output buf fer State Table (1/2) Output Buffer State TMP92CZ26A 92CZ26A-42 Table 3.3.8 Output buf fer state table (2/2) 3.4 Boot ROM 3.4.1 Operation Modes TMP92CZ26A 92CZ26A-44 3.4.2 Hardware Specifications of Internal Boot ROM TMP92CZ26A 92CZ26A-45 3.4.3 Outline of Boot Operation TMP92CZ26A 92CZ26A-46 TMP92CZ26A 92CZ26A-47 TMP92CZ26A 92CZ26A-48 Table 3.4.4 Recommended Pin Connections TMP92CZ26A 92CZ26A-49 TMP92CZ26A 92CZ26A-50 3.4.4 Downloading a User Program via UART TMP92CZ26A 92CZ26A-51 TMP92CZ26A 92CZ26A-52 TMP92CZ26A 92CZ26A-53 TMP92CZ26A 92CZ26A-54 TMP92CZ26A 92CZ26A-55 TMP92CZ26A 92CZ26A-56 Page TMP92CZ26A 92CZ26A-58 3.4.5 Downloading a User Program via USB TMP92CZ26A 92CZ26A-59 TMP92CZ26A 92CZ26A-60 TMP92CZ26A 92CZ26A-61 TMP92CZ26A 92CZ26A-62 TMP92CZ26A 92CZ26A-63 TMP92CZ26A 92CZ26A-64 TMP92CZ26A 92CZ26A-65 Page TMP92CZ26A 92CZ26A-67 3.5 Interrupts TMP92CZ26A 92CZ26A-68 TMP92CZ26A 92CZ26A-69 3.5.1 General-purpose Interrupt Processing TMP92CZ26A 92CZ26A-70 to Vector Value Address Refer Micro DMA Request Vector TMP92CZ26A 92CZ26A-71 TMP92CZ26A 92CZ26A-72 3.5.2 Micro DMA processing TMP92CZ26A 92CZ26A-73 TMP92CZ26A 92CZ26A-74 TMP92CZ26A 92CZ26A-75 (4) Detailed description of the transf er mode register 0 0 0 Mode DMAM0 to 7 ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = Reserved TMP92CZ26A 92CZ26A-76 3.5.3 Interrupt Controller Operation TMP92CZ26A 92CZ26A-77 Figure 3.5.3 Block Diagram of Interrupt Controller TMP92CZ26A 92CZ26A-78 TMP92CZ26A 92CZ26A-79 TMP92CZ26A 92CZ26A-80 TMP92CZ26A 92CZ26A-81 Interrupt request flag R R/W R R/W TMP92CZ26A 92CZ26A-82 Symbol Name Address 7 6 5 4 3 2 1 0 DI TMP92CZ26A 92CZ26A-83 TMP92CZ26A 92CZ26A-84 TMP92CZ26A 92CZ26A-85 Symbol NAME Address Page TMP92CZ26A 92CZ26A-87 TMP92CZ26A 92CZ26A-88 3.6 DMAC (DMA Controller) Page TMP92CZ26A 92CZ26A-90 3.6.2 SFRs HDMASn Register 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 TMP92CZ26A 92CZ26A-91 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 TMP92CZ26A 92CZ26A-92 TMP92CZ26A 92CZ26A-93 TMP92CZ26A 92CZ26A-94 Figure 3.6.6 HDMAMn Register TMP92CZ26A 92CZ26A-95 TMP92CZ26A 92CZ26A-96 3.6.3 DMAC Operation Description Page TMP92CZ26A 92CZ26A-98 3.6.4 Setting Example Page TMP92CZ26A 92CZ26A-100 3.6.6 Considerations for Using More Than One Bus Master TMP92CZ26A 92CZ26A-101 Sample 1) Calculation example for CPU + HDMA TMP92CZ26A 92CZ26A-102 TMP92CZ26A 92CZ26A-103 Sample2) Calculation examples for CPU + LDMA TMP92CZ26A 92CZ26A-104 TMP92CZ26A 92CZ26A-105 Sample3) Calculation example for CPU + LDMA + ARDMA TMP92CZ26A 92CZ26A-106 TMP92CZ26A 92CZ26A-107 Sample 4) Calculation example for CPU + LDMA+ ARD MA + HDMA TMP92CZ26A 92CZ26A-108 TMP92CZ26A 92CZ26A-109 Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA at same time (Worst case) TMP92CZ26A 3.7 Function of ports Port 7 P76 1 I/O Port 8 P87 1 Output TMP92CZ26A 92CZ26A-111 Table 3.7.1 Port Functions (2/3) TMP92CZ26A 92CZ26A-112 Table 3.7.1 Port Functions (3/3) TMP92CZ26A 92CZ26A-113 T able 3.7.2 I/O Port and Specifications (1/4) TMP92CZ26A 92CZ26A-114 T able3.7.2 I I/O Port and Specifications (2/4) TMP92CZ26A 92CZ26A-115 T able3.7.2 I/O Port and Specifications (3/4) ALARM MLDALM TMP92CZ26A 92CZ26A-116 T able 3.7.2 I/O Port and Specifications (4/4) TMP92CZ26A 92CZ26A-117 3.7.1 Port 1 (P10 to P17) TMP92CZ26A 92CZ26A-118 Figure 3.7.2 Register for Port1 TMP92CZ26A 92CZ26A-119 3.7.2 Port 4 (P40 to P47) TMP92CZ26A 92CZ26A-120 Figure 3.7.4 Register for Port1r TMP92CZ26A 92CZ26A-121 3.7.3 Port 5 (P50 to P57) TMP92CZ26A 92CZ26A-122 Figure 3.7.6 Register for Port5 TMP92CZ26A 92CZ26A-123 3.7.4 Port 6 (P60 to P67) TMP92CZ26A 92CZ26A-124 Figure 3.7.8 Register for Port6 TMP92CZ26A 92CZ26A-125 3.7.5 Port 7 (P70 to P76) TMP92CZ26A 92CZ26A-126 TMP92CZ26A 92CZ26A-127 Figure 3.7.11 Register for Port7 TMP92CZ26A 92CZ26A-128 3.7.6 Port 8 (P80 to P87) TMP92CZ26A 92CZ26A-129 7 6 5 4 3 2 1 0 Figure 3.7.13 Register for Port 8 TMP92CZ26A 92CZ26A-130 3.7.7 Port 9 (P90 to P92, P96, P97) TMP92CZ26A 92CZ26A-131 TMP92CZ26A 92CZ26A-132 7 6 5 4 3 2 1 0 Figure 3.7.17 Register for Port 9 TMP92CZ26A 92CZ26A-133 3.7.8 Port A (PA0 to PA7) TMP92CZ26A 92CZ26A-134 TMP92CZ26A 92CZ26A-135 3.7.9 Port C (PC0 to PC7) TMP92CZ26A 92CZ26A-136 TMP92CZ26A 92CZ26A-137 TMP92CZ26A 92CZ26A-138 7 6 5 4 3 2 1 0 Figure 3.7.24 Register for Port C TMP92CZ26A 92CZ26A-139 3.7.10 Port F (PF0 to PF5, PF7) TMP92CZ26A 92CZ26A-140 TMP92CZ26A 92CZ26A-141 TMP92CZ26A 92CZ26A-142 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-143 3.7.11 Port G (PG0 to PG5) TMP92CZ26A 92CZ26A-144 7 6 5 4 3 2 1 0 Figure 3.7.30 Register for Port G TMP92CZ26A 92CZ26A-145 3.7.12 Port J (PJ0 to PJ7) TMP92CZ26A 92CZ26A-146 TMP92CZ26A 92CZ26A-147 7 6 5 4 3 2 1 0 Figure 3.7.33 Register for Port J TMP92CZ26A 92CZ26A-148 3.7.13 Port K (PK0 to PK7) TMP92CZ26A 92CZ26A-149 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3.7.35 Register for Port K TMP92CZ26A 92CZ26A-150 3.7.14 Port L (PL0 to PL7) TMP92CZ26A 92CZ26A-151 7 6 5 4 3 2 1 0 Figure 3.7.37 Register for Port L TMP92CZ26A 92CZ26A-152 3.7.15 Port M (PM1, PM2, PM7) TMP92CZ26A 92CZ26A-153 TMP92CZ26A 92CZ26A-154 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-155 3.7.16 Port N (PN0 to PN7) TMP92CZ26A 92CZ26A-156 7 6 5 4 3 2 1 0 Figure 3.7.43 Register for Port N TMP92CZ26A 92CZ26A-157 3.7.17 Port P (PP1 to PP7) TMP92CZ26A 92CZ26A-158 TMP92CZ26A 92CZ26A-159 TMP92CZ26A 92CZ26A-160 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-161 3.7.18 Port R (R0 to R3) TMP92CZ26A 92CZ26A-162 TMP92CZ26A 92CZ26A-163 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3.7.51 Register for Port R TMP92CZ26A 92CZ26A-164 3.7.19 Port T (PT0 to PT7) TMP92CZ26A 92CZ26A-165 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-166 3.7.20 Port U (PU0 to PU7) TMP92CZ26A 92CZ26A-167 TMP92CZ26A 92CZ26A-168 7 6 5 4 3 2 1 0 Figure 3.7.56 Register for Port U TMP92CZ26A 92CZ26A-169 3.7.21 Port V (PV0 to PV4, PV6, PV7) TMP92CZ26A 92CZ26A-170 TMP92CZ26A 92CZ26A-171 7 6 5 4 3 2 1 0 Figure 3.7.60 Register for Port V TMP92CZ26A 92CZ26A-172 3.7.22 Port W (PW0 to PW7) TMP92CZ26A 92CZ26A-173 7 6 5 4 3 2 1 0 Figure 3.7.62 Register for Port W TMP92CZ26A 92CZ26A-174 3.7.23 Port X (PX4, PX5 and PX7) TMP92CZ26A 92CZ26A-175 TMP92CZ26A 92CZ26A-176 7 6 5 4 3 2 1 0 Figure 3.7.65 Register for Port X TMP92CZ26A 92CZ26A-177 3.7.24 Port Z (PZ0 to PZ7) TMP92CZ26A 92CZ26A-178 TMP92CZ26A 92CZ26A-179 7 6 5 4 3 2 1 0 Figure 3.7.68 Register for Port Z TMP92CZ26A 3.8 Memory Controller (MEMC) 3.8.1 Functions Page TMP92CZ26A 92CZ26A-182 Table 3.8.1 Control register TMP92CZ26A 92CZ26A-183 Table 3.8.2 Control register TMP92CZ26A 92CZ26A-184 TMP92CZ26A 92CZ26A-185 3.8.3 Basic functions and register setting TMP92CZ26A 92CZ26A-186 TMP92CZ26A 92CZ26A-187 Page TMP92CZ26A 92CZ26A-189 TMP92CZ26A 92CZ26A-190 TMP92CZ26A 92CZ26A-191 TMP92CZ26A 92CZ26A-192 TMP92CZ26A 92CZ26A-193 Page TMP92CZ26A 92CZ26A-195 Page Page TMP92CZ26A 92CZ26A-198 Figure 3.8.4 Example of External 16-Bit SRAM and NOR Flash Connection TMP92CZ26A 92CZ26A-199 3.8.4 ROM Page mode Access Control Page TMP92CZ26A 92CZ26A-201 7 6 5 4 3 2 1 0 Page TMP92CZ26A 92CZ26A-203 CSZA to CSZD pins dont become to active. Figure 3.8.8 Recommended CS3 setting 3.9 External Memory Extension Function (MMU) 3.9.1 Recommended memory map TMP92CZ26A 92CZ26A-205 Figure 3.9.1Recommendation memory map for maximum specification (Logical address) TMP92CZ26A 92CZ26A-206 LOCAL-X LOCAL-Y LOCAL-Z 92CZ26 TMP92CZ26A 92CZ26A-207 A Figure 3.9.4 Recommendation memory map for simple system (P hysical address) TMP92CZ26A 92CZ26A-208 3.9.2 Control register TMP92CZ26A 92CZ26A-209 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-210 TMP92CZ26A 92CZ26A-211 TMP92CZ26A 92CZ26A-212 TMP92CZ26A 92CZ26A-213 TMP92CZ26A 92CZ26A-214 TMP92CZ26A 92CZ26A-215 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 TMP92CZ26A 92CZ26A-216 TMP92CZ26A 92CZ26A-217 TMP92CZ26A 92CZ26A-218 3.9.3 Setting example TMP92CZ26A 92CZ26A-219 (b) Sub routine (Bank-0 in LOCAL-Y) 3.10 SDRAM Controller (SDRAMC) TMP92CZ26A 92CZ26A-221 3.10.1 Control Registers The SDRAMC has the fol lo wing control registers. TMP92CZ26A 92CZ26A-222 Figure 3.10.1 Control Registers TMP92CZ26A 92CZ26A-223 3.10.2 Operation Description TMP92CZ26A 92CZ26A-224 TMP92CZ26A 92CZ26A-225 Figure3.10.2 1-Word Read Cycle Timing Figure3.10.3 Full-Page Read Cycle Timing TMP92CZ26A 92CZ26A-226 Figure3.10.4 Single Write Cycle Timing Figure3.10.5 Burst Write Cycle Timing TMP92CZ26A 92CZ26A-227 TMP92CZ26A 92CZ26A-228 TMP92CZ26A 92CZ26A-229 TMP92CZ26A 92CZ26A-230 TMP92CZ26A 92CZ26A-231 TMP92CZ26A 92CZ26A-232 TMP92CZ26A 92CZ26A-233 TMP92CZ26A 92CZ26A-234 TMP92CZ26A 92CZ26A-235 Data Bus Width 16 bits : Command address pin of SDRAM TMP92CZ26A 92CZ26A-236 3.10.3 An Example of Calculating HDMA Transfer Time TMP92CZ26A 92CZ26A-237 3.10.4 Considerations for Using the SDRAMC TMP92CZ26A 92CZ26A-238 3.11 NAND Flash Controller (NDFC) 3.11.1 Features TMP92CZ26A 92CZ26A-239 3.11.1 Block Diagram TMP92CZ26A 92CZ26A-240 3.11.2 Operation Description TMP92CZ26A 92CZ26A-241 TMP92CZ26A 92CZ26A-242 3.11.3 ECC Control TMP92CZ26A 92CZ26A-243 TMP92CZ26A 92CZ26A-244 TMP92CZ26A 92CZ26A-245 TMP92CZ26A 92CZ26A-246 3.11.4 Description of Registers NAND Flash Control 0 Registe r TMP92CZ26A 92CZ26A-247 TMP92CZ26A 92CZ26A-248 TMP92CZ26A 92CZ26A-249 NAND Flash Control 1 Register Page TMP92CZ26A 92CZ26A-251 Page TMP92CZ26A 92CZ26A-253 NAND Flash ECC Register 0 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 TMP92CZ26A 92CZ26A-254 TMP92CZ26A 92CZ26A-255 NAND Flash Reed-Solomon Calculation Result Address Register Figure 3.11.8 NAND Flash Reed-Solomon Calculation Result Address Registe r TMP92CZ26A 92CZ26A-256 TMP92CZ26A 92CZ26A-257 3.11.5 An Example of Accessing NAND Flash of SLC Type TMP92CZ26A 92CZ26A-258 TMP92CZ26A 92CZ26A-259 Page TMP92CZ26A 92CZ26A-261 TMP92CZ26A 92CZ26A-262 TMP92CZ26A 92CZ26A-263 Page TMP92CZ26A 92CZ26A-265 3.11.7 An Example of Connections with NAND Flash TMP92CZ26A 92CZ26A-266 3.12 8 Bit Timer (TMRA) Page Page Page TMP92CZ26A 92CZ26A-270 TMP92CZ26A 92CZ26A-271 3.12.2 Operation of Each Circuit Page TMP92CZ26A 92CZ26A-273 Page Page TMP92CZ26A 92CZ26A-276 Figure 3.12.8 Register for TMRA (4 ) TMP92CZ26A 92CZ26A-277 Figure 3.12.9 Register for TMRA (5 ) TMP92CZ26A 92CZ26A-278 Figure 3.12.10 Register for TMRA (6) TMP92CZ26A 92CZ26A-279 Figure 3.12.11 Register for TMRA (7) TMP92CZ26A 92CZ26A-280 Figure 3.12.12 Register for TMRA (8) TMP92CZ26A 92CZ26A-281 Figure 3.12.13 Register for TMRA (9) TMP92CZ26A 92CZ26A-282 Figure 3.12.14 Register for TMRA (10) TMP92CZ26A 92CZ26A-283 Figure 3.12.15 Register for TMRA (11) TMP92CZ26A 92CZ26A-284 Figure 3.12.16 TMRA Registers TMP92CZ26A 92CZ26A-285 3.12.4 Operation in Each Mode TMP92CZ26A 92CZ26A-286 Figure 3.12.17 Square Wave Output Timing Chart (50% duty) TMP92CZ26A 92CZ26A-287 TMP92CZ26A 92CZ26A-288 Page TMP92CZ26A 92CZ26A-290 Example: To generate 1/4 duty 31.25 kHz pulses (at fC= 50 MHz) Page TMP92CZ26A 92CZ26A-292 Figure 3.12.25 Register Buffer Operation Example: T o output the foll ow ing PWM waves o n the T A1OUT pin (at f TMP92CZ26A 92CZ26A-293 Table 3.12.3 PWM Cycle (5) Settings for each mode Table 3.12.4 shows the SFR settings for eac h mode. Table 3.12.4 Timer Mode Setting Registers 3.13 16 bit timer / Event counter (TMRB) Page TMP92CZ26A 92CZ26A-296 Figure 3.13.2 Block diagram of TMRB1 TMP92CZ26A 3.13.2 Operation TMP92CZ26A 92CZ26A-298 TMP92CZ26A 92CZ26A-299 TMP92CZ26A 92CZ26A-300 TMP92CZ26A 92CZ26A-301 TMP92CZ26A 92CZ26A-302 3.13.3 SFR 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-303 Figure 3.13.4 Register for TMRB (2 ) TMP92CZ26A 92CZ26A-304 Figure 3.13.5 Register for TMRB (3 ) TMP92CZ26A 92CZ26A-305 Figure 3.13.6 Register for TMRB (4 ) Page TMP92CZ26A 92CZ26A-307 Figure 3.13.8 Register for TMRB (6 ) TMP92CZ26A 92CZ26A-308 3.13.4 Operation in Each Mode TMP92CZ26A 92CZ26A-309 TMP92CZ26A 92CZ26A-310 The following block diagram illustrates this m ode. X: Don't care, : No change TMP92CZ26A 92CZ26A-311 TMP92CZ26A 92CZ26A-312 Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0pin Page Page Page TMP92CZ26A 92CZ26A-316 3.14.1 Block Diagram Figure 3.14.2 Block Diagram TMP92CZ26A 92CZ26A-317 3.14.2 Operation of Each Circuit TMP92CZ26A 92CZ26A-318 TMP92CZ26A 92CZ26A-319 TMP92CZ26A 92CZ26A-320 Calculation method the frequency of TA0TRG Frequency of TA0TRG = Baud rate 16 TMP92CZ26A 92CZ26A-321 TMP92CZ26A 92CZ26A-322 Page Page TMP92CZ26A 92CZ26A-325 Page TMP92CZ26A 92CZ26A-327 TMP92CZ26A 92CZ26A-328 3.14.3 SFR 7 6 5 4 3 2 1 0 Figure 3.14.6 Serial Mode Control Register (ch annel 0, SC0MOD0) TMP92CZ26A 92CZ26A-329 7 6 5 4 3 2 1 0 Figure 3.14.7 Serial Control Register (ch annel 0, SC0CR) TMP92CZ26A 92CZ26A-330 7 6 5 4 3 2 1 0 Figure 3.14.8 Baud rate generator control (channel 0, BR0CR, BR0ADD) 7 6 5 4 3 2 1 0 Page Page Page Page TMP92CZ26A 92CZ26A-335 INTTX0 interrupt routine TMP92CZ26A 92CZ26A-336 2 TMP92CZ26A 92CZ26A-337 Page Page Page Page Page TMP92CZ26A 92CZ26A-343 7 6 5 4 3 2 1 0 Figure 3.14.21 IrDA Control Regi ster TMP92CZ26A 3.15 Serial Bus Interface (SBI) 3.15.1 Configuration TMP92CZ26A 92CZ26A-345 3.15.2 Serial Bus Interface (SBI) Control 3.15.3 The Data Formats in the I2C Bus Mode TMP92CZ26A 92CZ26A-346 3.15.4 I2C Bus Mode Control Register TMP92CZ26A 92CZ26A-347 Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Figure 3.15.4 Registers for the I2C bus mode TMP92CZ26A 92CZ26A-348 Serial Bus Interface Control Register 1 Figure 3.15.5 Registers for the I2C bus mode Table 3.15.1Resolution of base clock TMP92CZ26A 92CZ26A-349 Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 Figure 3.15.6 Registers for the I2C bus mode TMP92CZ26A 92CZ26A-350 TMP92CZ26A 92CZ26A-351 3.15.5 Control in I2C Bus Mode TMP92CZ26A 92CZ26A-352 TMP92CZ26A 92CZ26A-353 TMP92CZ26A 92CZ26A-354 TMP92CZ26A 92CZ26A-355 TMP92CZ26A 92CZ26A-356 TMP92CZ26A 92CZ26A-357 3.15.6 Data Transfer in I2C Bus Mode TMP92CZ26A 92CZ26A-358 TMP92CZ26A 92CZ26A-359 TMP92CZ26A 92CZ26A-360 TMP92CZ26A 92CZ26A-361 TMP92CZ26A 92CZ26A-362 TMP92CZ26A 92CZ26A-363 Table 3.15.2 Operation in the slave m od e <TRX> <AL> <AAS> <AD0> Conditions Process TMP92CZ26A 92CZ26A-364 TMP92CZ26A 92CZ26A-365 TMP92CZ26A 92CZ26A-366 3.16 USB Controller 3.16.1 Outline TMP92CZ26A 92CZ26A-367 TMP92CZ26A 92CZ26A-368 TMP92CZ26A 92CZ26A-369 3.16.2 900/H1 CPU I/F TMP92CZ26A 92CZ26A-370 TMP92CZ26A 92CZ26A-371 TMP92CZ26A 92CZ26A-372 TMP92CZ26A 92CZ26A-373 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 EPx_FULL_A/B: TMP92CZ26A 92CZ26A-374 TMP92CZ26A 92CZ26A-375 TMP92CZ26A 92CZ26A-376 TMP92CZ26A 92CZ26A-377 TMP92CZ26A 92CZ26A-378 TMP92CZ26A 92CZ26A-379 3.16.3 UDC CORE TMP92CZ26A 92CZ26A-380 Figure 3.16.3 UDC CORE SFRs (1/3) Address Read/Write SFR Symbol Note: * is not used at TMP92CZ26A. TMP92CZ26A 92CZ26A-381 Figure 3.16.4 UDC CORE SFRs (2/3) Address Read/Write SFR Symbol Note: * is not used at TMP92CZ26A. Page TMP92CZ26A 92CZ26A-383 TMP92CZ26A 92CZ26A-384 TMP92CZ26A 92CZ26A-385 TMP92CZ26A 92CZ26A-386 TMP92CZ26A 92CZ26A-387 TMP92CZ26A 92CZ26A-388 Page TMP92CZ26A 92CZ26A-390 TMP92CZ26A 92CZ26A-391 STATUS [2:0] (Bit4 to bit2) f TMP92CZ26A 92CZ26A-392 TMP92CZ26A 92CZ26A-393 TMP92CZ26A 92CZ26A-394 TMP92CZ26A 92CZ26A-395 TMP92CZ26A 92CZ26A-396 TMP92CZ26A 92CZ26A-397 TMP92CZ26A 92CZ26A-398 TMP92CZ26A 92CZ26A-399 TMP92CZ26A 92CZ26A-400 TMP92CZ26A 92CZ26A-401 EP [2:0 ] (Bit6 to bit4) COMMAND [3:0] (Bit3 to bit0) TMP92CZ26A 92CZ26A-402 TMP92CZ26A 92CZ26A-403 TMP92CZ26A 92CZ26A-404 TMP92CZ26A 92CZ26A-405 TMP92CZ26A 92CZ26A-406 TMP92CZ26A 92CZ26A-407 TMP92CZ26A 92CZ26A-408 3.16.4 Descriptor RAM TMP92CZ26A 92CZ26A-409 Descriptor RAM setting example: Address Data Description Description TMP92CZ26A 92CZ26A-410 Address Data Description Description TMP92CZ26A 92CZ26A-411 Address DATA Description Description TMP92CZ26A 92CZ26A-412 3.16.5 Device Request TMP92CZ26A 92CZ26A-413 TMP92CZ26A 92CZ26A-414 TMP92CZ26A 92CZ26A-415 TMP92CZ26A 92CZ26A-416 TMP92CZ26A 92CZ26A-417 TMP92CZ26A 92CZ26A-418 TMP92CZ26A 92CZ26A-419 Below is control flow in UDC watch from application. Figure 3.16.6 Control Flow in UDC Watch from Application TMP92CZ26A 92CZ26A-420 3.16.6 Transfer mode and Protocol Transaction TMP92CZ26A 92CZ26A-421 TMP92CZ26A 92CZ26A-422 TMP92CZ26A 92CZ26A-423 TMP92CZ26A 92CZ26A-424 TMP92CZ26A 92CZ26A-425 TMP92CZ26A 92CZ26A-426 TMP92CZ26A 92CZ26A-427 TMP92CZ26A 92CZ26A-428 TMP92CZ26A 92CZ26A-429 Figure 3.16.9 Control Flow in UDC (Set up stage) TMP92CZ26A 92CZ26A-430 TMP92CZ26A 92CZ26A-431 TMP92CZ26A 92CZ26A-432 TMP92CZ26A 92CZ26A-433 TMP92CZ26A 92CZ26A-434 TMP92CZ26A 92CZ26A-435 TMP92CZ26A 92CZ26A-436 TMP92CZ26A 92CZ26A-437 TMP92CZ26A 92CZ26A-438 Figure 3.16.13 Control Flow in UDC (Isochronous transfer type (Transmission)) TMP92CZ26A 92CZ26A-439 Page TMP92CZ26A 92CZ26A-441 Page TMP92CZ26A 92CZ26A-443 TMP92CZ26A 92CZ26A-444 TMP92CZ26A 92CZ26A-445 TMP92CZ26A 92CZ26A-446 TMP92CZ26A 92CZ26A-447 TMP92CZ26A 92CZ26A-448 3.16.8 USB Device answer TMP92CZ26A 92CZ26A-449 TMP92CZ26A 92CZ26A-450 3.16.9 Power Management Page TMP92CZ26A 92CZ26A-452 3.16.10 Supplement (1) External access flow to USB communication a) Normally movement TMP92CZ26A 92CZ26A-453 Page TMP92CZ26A 92CZ26A-455 TMP92CZ26A 92CZ26A-456 (c) Device request and variou s request judgment TMP92CZ26A 92CZ26A-457 TMP92CZ26A 92CZ26A-458 TMP92CZ26A 92CZ26A-459 TMP92CZ26A 92CZ26A-460 (c-4) SET_CONFIGRATION request transaction Page TMP92CZ26A 92CZ26A-462 (c-6) SET_INTERFACE request transaction TMP92CZ26A 92CZ26A-463 TMP92CZ26A 92CZ26A-464 TMP92CZ26A 92CZ26A-465 (c-10) GET_DESCRIPTOR req u est transaction TMP92CZ26A 92CZ26A-466 TMP92CZ26A 92CZ26A-467 (c-12) Data write transaction to FIFO by EP0 TMP92CZ26A 92CZ26A-468 TMP92CZ26A 92CZ26A-469 TMP92CZ26A 92CZ26A-470 TMP92CZ26A 92CZ26A-471 TMP92CZ26A 92CZ26A-472 TMP92CZ26A 92CZ26A-473 TMP92CZ26A 92CZ26A-474 TMP92CZ26A 92CZ26A-475 3.16.11 Points to Note and Restrictions TMP92CZ26A 92CZ26A-476 Page Page TMP92CZ26A 92CZ26A-479 3.17.2 SFR 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 TMP92CZ26A 92CZ26A-480 TMP92CZ26A 92CZ26A-481 TMP92CZ26A 92CZ26A-482 (2) SPICT(SPI Control Register) SPICT register is for data length or CRC etc. (823H) SPICT Register TMP92CZ26A 92CZ26A-483 TMP92CZ26A 92CZ26A-484 TMP92CZ26A 92CZ26A-485 TMP92CZ26A 92CZ26A-486 TMP92CZ26A 92CZ26A-487 TMP92CZ26A 92CZ26A-488 TMP92CZ26A 92CZ26A-489 TMP92CZ26A 92CZ26A-490 TMP92CZ26A 92CZ26A-491 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Page TMP92CZ26A 92CZ26A-493 (5) SPITD (SPI Transmit Data Register) SPITD0, SPITD1 registers are for writing transmit ted data. Figure 3.17.12 SPITD Register TMP92CZ26A 92CZ26A-494 (6) SPIRD (SPI Receiv e Data Register) SPIRD0, SPIRD1 registers are for reading received data. Figure 3.17.13 SPIRD register 92CZ26A-495 Note of FIFO buffer TMP92CZ26A 92CZ26A-496 3.18 I2S (Inter-IC Sound) TMP92CZ26A 92CZ26A-497 3.18.1 Block Diagram TMP92CZ26A 92CZ26A-498 3.18.2 SFRs Figure 3.18.2 I2S Channel 0 Control Re gisters TMP92CZ26A Figure 3.18.3 I2S Channel 1 Control Re gisters TMP92CZ26A 92CZ26A-500 3.18.3 Description of Operation Page TMP92CZ26A 92CZ26A-502 TMP92CZ26A 92CZ26A-503 TMP92CZ26A 92CZ26A-504 When I2SnCTL<WLVLn> = 0 When I2SnCTL<WLVLn> = 1 TMP92CZ26A 92CZ26A-505 3.18.4 Detailed Description of Operation TMP92CZ26A 92CZ26A-506 TMP92CZ26A 92CZ26A-507 TMP92CZ26A 92CZ26A-508 3.19 LCD Controller (LCDC) TMP92CZ26A 92CZ26A-509 3.19.1 LCDC Features according to LCD Driver Type TMP92CZ26A 92CZ26A-510 3.19.2 SFRs TMP92CZ26A 92CZ26A-511 TMP92CZ26A 92CZ26A-512 TMP92CZ26A 92CZ26A-513 TMP92CZ26A 92CZ26A-514 TMP92CZ26A 92CZ26A-515 TMP92CZ26A 92CZ26A-516 TMP92CZ26A 92CZ26A-517 3.19.3 Description of Operation TMP92CZ26A 92CZ26A-518 TMP92CZ26A 92CZ26A-519 TMP92CZ26A 92CZ26A-520 TMP92CZ26A 92CZ26A-521 TMP92CZ26A 92CZ26A-522 TMP92CZ26A 92CZ26A-523 TMP92CZ26A 92CZ26A-524 TMP92CZ26A 92CZ26A-525 TMP92CZ26A 92CZ26A-526 TMP92CZ26A 92CZ26A-527 TMP92CZ26A 92CZ26A-528 TMP92CZ26A 92CZ26A-529 TMP92CZ26A 92CZ26A-530 TMP92CZ26A 92CZ26A-531 TMP92CZ26A 92CZ26A-532 TMP92CZ26A 92CZ26A-533 TMP92CZ26A 92CZ26A-534 TMP92CZ26A 92CZ26A-535 TMP92CZ26A 92CZ26A-536 TMP92CZ26A 92CZ26A-537 TMP92CZ26A 92CZ26A-538 TMP92CZ26A 92CZ26A-539 TMP92CZ26A 92CZ26A-540 TMP92CZ26A 92CZ26A-541 TMP92CZ26A 92CZ26A-542 TMP92CZ26A 92CZ26A-543 TMP92CZ26A 92CZ26A-544 TMP92CZ26A 92CZ26A-545 TMP92CZ26A 92CZ26A-546 TMP92CZ26A 92CZ26A-547 TMP92CZ26A 92CZ26A-548 TMP92CZ26A 92CZ26A-549 TMP92CZ26A 92CZ26A-550 Page TMP92CZ26A 92CZ26A-552 3.19.4 Interrupt Function TMP92CZ26A 92CZ26A-553 3.19.5 Special Functions TMP92CZ26A 92CZ26A-554 The table below shows the HOT point locations that can be specified. The table below shows the HOT point segment and common sizes that can be specified. TMP92CZ26A 92CZ26A-555 TMP92CZ26A 92CZ26A-556 TMP92CZ26A 92CZ26A-557 TMP92CZ26A 92CZ26A-558 TMP92CZ26A 92CZ26A-559 TMP92CZ26A 92CZ26A-560 TMP92CZ26A 92CZ26A-561 TMP92CZ26A 92CZ26A-562 3.19.6 Setting Example STN TMP92CZ26A 92CZ26A-563 TFT 3.20 Touch Screen Interface (TSI) 3.20.1 Touch-Screen Interface Module Internal/External Connection TMP92CZ26A 92CZ26A-565 3.20.2 Touch Screen Interface (TSI) Control Register TSI control register Page TMP92CZ26A 92CZ26A-567 TMP92CZ26A 92CZ26A-568 3.20.4 X/Y position measuring procedure Page TMP92CZ26A 92CZ26A-570 TMP92CZ26A 92CZ26A-571 (b) X position measurement (Start AD conversion) Internal data bus Page Page TMP92CZ26A 92CZ26A-574 3.21 Real time clock (RTC) 3.21.1 Function description for RTC 3.21.2 Block diagram TMP92CZ26A 92CZ26A-575 3.21.3 Control registers Table 3.21.1 PAGE 0 (Timer function) registers TMP92CZ26A 92CZ26A-576 3.21.4 Detailed explanation of control register TMP92CZ26A 92CZ26A-577 TMP92CZ26A 92CZ26A-578 TMP92CZ26A 92CZ26A-579 TMP92CZ26A 92CZ26A-580 TMP92CZ26A 92CZ26A-581 TMP92CZ26A 92CZ26A-582 (10) PAGE register (for PAGE0/1) 7 6 5 4 3 2 1 0 (11) Reset register (for PAGE0/1) 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-583 3.21.5 Operational description TMP92CZ26A 92CZ26A-584 TMP92CZ26A 92CZ26A-585 TMP92CZ26A 92CZ26A-586 TMP92CZ26A 92CZ26A-587 3.21.6 Explanation of the interrupt signal and alarm signal Page TMP92CZ26A 92CZ26A-589 3.22 Melody / Alarm generator (MLD) TMP92CZ26A 92CZ26A-590 3.22.1 Block Diagram TMP92CZ26A 92CZ26A-591 3.22.2 Control registers ALM register 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-592 3.22.3 Operational Description TMP92CZ26A 92CZ26A-593 TMP92CZ26A 92CZ26A-594 Example: Waveform of alarm pattern for each setting value: not invert) TMP92CZ26A 92CZ26A-595 3.23 Analog-Digital Converter (ADC) TMP92CZ26A 92CZ26A-596 3.23.1 Control register Figure 3.23.2 AD Conversion Registers TMP92CZ26A 92CZ26A-597 TMP92CZ26A 92CZ26A-598 TMP92CZ26A 92CZ26A-599 TMP92CZ26A 92CZ26A-600 TMP92CZ26A 92CZ26A-601 TMP92CZ26A 92CZ26A-602 TMP92CZ26A 92CZ26A-603 TMP92CZ26A 92CZ26A-604 TMP92CZ26A 92CZ26A-605 TMP92CZ26A 92CZ26A-606 3.23.2 Operation TMP92CZ26A 92CZ26A-607 3.23.2.3 TMP92CZ26A 92CZ26A-608 TMP92CZ26A 92CZ26A-609 TMP92CZ26A 92CZ26A-610 TMP92CZ26A 92CZ26A-611 Page TMP92CZ26A 92CZ26A-613 TMP92CZ26A 92CZ26A-614 TMP92CZ26A 92CZ26A-615 3.24 Watchdog Timer (Runaway detection timer) 3.24.1 Configuration TMP92CZ26A 92CZ26A-616 3.24.2 Operation TMP92CZ26A 92CZ26A-617 3.24.3 Control Registers TMP92CZ26A 92CZ26A-618 7 6 5 4 3 2 1 0 Figure 3.24.4 Watchdog Timer Mo de Register 7 6 5 4 3 2 1 0 3.25 Power Management Circuit (PMC) TMP92CZ26A 92CZ26A-620 3.25.1 SFR TMP92CZ26A 92CZ26A-621 3.25.2 Detailed Description of Operation TMP92CZ26A 92CZ26A-622 TMP92CZ26A 92CZ26A-623 Source Symbol Note TMP92CZ26A 92CZ26A-624 3.25.3 Detailed Description of Timing Internal HOT_RESET assert to dead circuit only. (DVCC1A &DVCC1C circuit) TMP92CZ26A 92CZ26A-625 TMP92CZ26A 92CZ26A-626 3.25.4 Notes of Power sequence TMP92CZ26A 92CZ26A-627 3.25.5 Setting Example TMP92CZ26A 92CZ26A-628 3.26 Multiply and Accumulate Calculation Unit (MAC) 3.26.1 Registers TMP92CZ26A 92CZ26A-629 3.26.1.2 Data Registers The data registers are arranged as shown below. TMP92CZ26A 92CZ26A-630 3.26.2 Description of Operation TMP92CZ26A 92CZ26A-631 TMP92CZ26A 92CZ26A-632 3.26.3 Operation Examples TMP92CZ26A 3.27 Debug Mode TMP92CZ26A 92CZ26A-634 TMP92CZ26A 92CZ26A-635 TMP92CZ26A 92CZ26A-636 TMP92CZ26A 92CZ26A-637 TMP92CZ26A 92CZ26A-638 TMP92CZ26A 92CZ26A-639 TMP92CZ26A 92CZ26A-640 4. Electrical Characteristics (Tentative) 4.1 Maximum Ratings TMP92CZ26A 92CZ26A-641 4.2 DC Electrical Characteristics Symbol Parameter Min Typ. Max Unit Condition TMP92CZ26A 92CZ26A-642 TMP92CZ26A 92CZ26A-643 TMP92CZ26A 92CZ26A-644 TMP92CZ26A 92CZ26A-645 4.3 AC Characteristics 4.3.1 Basic Bus Cycle TMP92CZ26A 92CZ26A-646 Write cycle Variable No. Parameter Symbol Min Max 80MHz 60MHz Unit TMP92CZ26A 92CZ26A-647 TMP92CZ26A 92CZ26A-648 TMP92CZ26A 92CZ26A-649 TMP92CZ26A 92CZ26A-650 4.3.2 Page ROM Read Cycle TMP92CZ26A 92CZ26A-651 4.3.3 SDRAM controller AC Characteristics TMP92CZ26A 92CZ26A-652 TMP92CZ26A 92CZ26A-653 TMP92CZ26A 92CZ26A-654 TMP92CZ26A 92CZ26A-655 TMP92CZ26A 92CZ26A-656 TMP92CZ26A 92CZ26A-657 TMP92CZ26A 92CZ26A-658 4.3.4 NAND Flash Controller AC Characteristics TMP92CZ26A 92CZ26A-659 4.3.5 Serial channel timing TMP92CZ26A 92CZ26A-660 4.3.6 Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0) 4.3.7 Interrupt Operation 4.3.8 USB Timing (Full-speed) TMP92CZ26A 92CZ26A-661 4.3.9 LCD Controller TMP92CZ26A 92CZ26A-662 4.3.10 I2S Timing TMP92CZ26A 92CZ26A-663 4.3.11 SPI Controller TMP92CZ26A 4.4 AD Conversion Characteristics Parameter Symbol Condition Min Typ. Max Unit TMP92CZ26A 5. Table of Special function registers (SFRs) TMP92CZ26A 92CZ26A-666 Table 5.1 I/O Register Address Map [1] Port (1/2) TMP92CZ26A 92CZ26A-667 TMP92CZ26A 92CZ26A-668 [2] INTC [3] MEMC [4] TSI Note: Do not access no allocated name address. TMP92CZ26A 92CZ26A-669 [5] SDRAMC Address Name [6] LCDC [7] PMC TMP92CZ26A 92CZ26A-670 [8] USBC (1/2) Address Name Address Name Address Name Address Name TMP92CZ26A 92CZ26A-671 TMP92CZ26A 92CZ26A-672 [9] SPIC Address Name Address Name [10] MMU TMP92CZ26A 92CZ26A-673 TMP92CZ26A 92CZ26A-674 [12] DMAC Address Name Address Name Address Name Address Name TMP92CZ26A 92CZ26A-675 [13] CGEAR, PLL [14] 8-bit timer Address Name Address Name Address Name Address Name Address Name Address Name Address Name TMP92CZ26A 92CZ26A-676 TMP92CZ26A 92CZ26A-677 [22] I2S [23] MAC Note: Do not access no allocated name address. TMP92CZ26A 92CZ26A-678 (1) I/O ports (1/11) Symbol Name TMP92CZ26A 92CZ26A-679 (1) I/O ports (2/11) Symbol Name TMP92CZ26A 92CZ26A-680 (1) I/O ports (3/11) Symbol Name TMP92CZ26A 92CZ26A-681 (1) I/O ports (4/11) Symbol Name TMP92CZ26A 92CZ26A-682 (1) I/O ports (5/11) Symbol Name TMP92CZ26A 92CZ26A-683 (1) I/O ports (6/11) Symbol Name TMP92CZ26A 92CZ26A-684 (1) I/O ports (7/11) Symbol Name TMP92CZ26A 92CZ26A-685 (1) I/O ports (8/11) Symbol Name TMP92CZ26A 92CZ26A-686 (1) I/O ports (9/11) Symbol Name TMP92CZ26A 92CZ26A-687 (1) I/O ports (10/11) TMP92CZ26A 92CZ26A-688 (1) I/O ports (11/11) TMP92CZ26A 92CZ26A-689 (2) Interrupt control (1/4) TMP92CZ26A 92CZ26A-690 (2) Interrupt control (2/4) Symbol Name TMP92CZ26A 92CZ26A-691 (2) Interrupt control (3/4) Symbol Name TMP92CZ26A 92CZ26A-692 (2) Interrupt control (4/4) Symbol Name TMP92CZ26A 92CZ26A-693 (3) Memory controller (1/4) Symbol Name TMP92CZ26A 92CZ26A-694 (3) Memory controller (2/4) Symbol Name TMP92CZ26A 92CZ26A-695 (3) Memory controller (3/4) Symbol Name TMP92CZ26A 92CZ26A-696 (3) Memory controller (4/4) Symbol Name TMP92CZ26A 92CZ26A-697 (4) TSI Symbol Name TMP92CZ26A 92CZ26A-698 (5) SDRAM controller Symbol Name TMP92CZ26A 92CZ26A-699 (6) LCD controller (1/6) Symbol Name TMP92CZ26A 92CZ26A-700 (6) LCD controller (2/6) Symbol Name TMP92CZ26A 92CZ26A-701 (6) LCD controller (3/6) Symbol Name TMP92CZ26A 92CZ26A-702 (6) LCD controller (4/6) Symbol Name TMP92CZ26A 92CZ26A-703 (7) PMC Symbol Name TMP92CZ26A 92CZ26A-704 (8) USB controller (1/6) Symbol Name TMP92CZ26A 92CZ26A-705 (8) USB control ler (2/6) Symbol Name TMP92CZ26A 92CZ26A-706 (8) USB control ler (3/6) Symbol Name TMP92CZ26A 92CZ26A-707 (8) USB control ler (4/6) Symbol Name TMP92CZ26A 92CZ26A-708 (8) USB control ler (5/6) Symbol Name TMP92CZ26A 92CZ26A-709 (8) USB control ler (6/6) Symbol Name TMP92CZ26A 92CZ26A-710 (9) SPIC (1/2) Symbol Name TMP92CZ26A 92CZ26A-711 (9) SPIC (2/2) Symbol Name TMP92CZ26A 92CZ26A-712 (10) MMU (1/8) Symbol Name TMP92CZ26A 92CZ26A-713 (10) MMU (2/8) Symbol Name TMP92CZ26A 92CZ26A-714 (10) MMU (3/8) Symbol Name TMP92CZ26A 92CZ26A-715 (10) MMU (4/8) Symbol Name TMP92CZ26A 92CZ26A-716 (10) MMU (5/8) Symbol Name TMP92CZ26A 92CZ26A-717 (10) MMU (6/8) Symbol Name TMP92CZ26A 92CZ26A-718 (10) MMU (7/8) Symbol Name TMP92CZ26A 92CZ26A-719 (10) MMU (8/8) Symbol Name TMP92CZ26A 92CZ26A-720 (11) NAND-Flash contro ller (1/4) Symbol Name TMP92CZ26A 92CZ26A-721 (11) NAND-Flash contro ller (2/4) Symbol Name TMP92CZ26A 92CZ26A-722 (11) NAND-Flash contro ller (3/4) Symbol Name TMP92CZ26A 92CZ26A-723 (11) NAND-Flash contro ller (4/4) Symbol Name TMP92CZ26A 92CZ26A-724 (12) DMAC (1/7) Symbol Name TMP92CZ26A 92CZ26A-725 (12) DMAC (2/7) Symbol Name TMP92CZ26A 92CZ26A-726 (12) DMAC (3/7) Symbol Name TMP92CZ26A 92CZ26A-727 (12) DMAC (4/7) Symbol Name TMP92CZ26A 92CZ26A-728 (12) DMAC (5/7) Symbol Name TMP92CZ26A 92CZ26A-729 (12) DMAC (6/7) Symbol Name TMP92CZ26A 92CZ26A-730 (12) DMAC (7/7) Symbol Name TMP92CZ26A 92CZ26A-731 (13) Clock gear, PLL Symbol Name TMP92CZ26A 92CZ26A-732 (14) 8-bit timer (1/2) Symbol Name TMP92CZ26A 92CZ26A-733 (14) 8-bit timer (1/2) Symbol Name TMP92CZ26A 92CZ26A-734 (15) 16-bit timer (1/2) Symbol Name TMP92CZ26A 92CZ26A-735 (15) 16-bit timer (2/2) Symbol Name TMP92CZ26A 92CZ26A-736 (16) UART/Serial channel s Symbol Name TMP92CZ26A 92CZ26A-737 (17) SBI Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CZ26A 92CZ26A-738 (18) AD converter (1/3) Symbol Name TMP92CZ26A 92CZ26A-739 (18) AD converter (2/3) Symbol Name TMP92CZ26A 92CZ26A-740 (18) AD converter (3/3) Symbol Name ADMOD3 AD mode TMP92CZ26A 92CZ26A-741 (19) Watchdog timer Symbol Name TMP92CZ26A 92CZ26A-742 (20) RTC (Real-Time Clock) Symbol Name TMP92CZ26A 92CZ26A-743 (21) Melody/alarm generator Symbol Name TMP92CZ26A 92CZ26A-744 (22) I2S (1/2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMP92CZ26A 92CZ26A-745 (22) I2S (2/2) Symbol Name TMP92CZ26A 92CZ26A-746 (23) MAC (1/ 2 ) Symbol Name TMP92CZ26A 92CZ26A-747 (23) MAC (2/ 2 ) Symbol Name 6. Package