Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-184

TMP92CZ26A
92CZ26A-184
(2) Operation after releasing reset
The data bus width at starting is determined depending on state of AM1/AM0 pins after
releasing reset. Then, the external memory access as follows;
Note: A memory to be used to start afte r releasing reset is either N OR-Flash or Masked-ROM. NAND -Flash ,
SDRAM can’t be used.
AM1/AM0 pins are valid only just after releasing reset. In other cases, the data bus width
is the value set in the con trol register <BnBUS 1:0>.
After reset, only control register (B2CSH/B2CSL) of the block address area 2 is effective
automatically. (B2CSH<B2E> is set t o “1” b y reset).
The data bus width which is specified by AM1/AM0 pin is load ed to the bit to specify the
bus width of the control register in the block address area 2.
The block address area 2 is set to address 000000H to FFFFFFH by reset
(B2CSH<B2M> is reset to “0”) .
After releasing reset, the block address areas are specified by MSARn and MAMRn.
Then, set BnCS.
Set BnCSH<BnE> to “1” in order to enable the setting.
AM1 AM0 Start Mode
0 0 Don’t use this setting
0 1 Start with 16-bit data bus (note)
1 0 Don’t use this setting
1 1
Start with BOOT(32-bit internal-MROM )