Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-101

TMP92CZ26A
92CZ26A-101
Sample 1) Calculation example for CPU + HDMA
Conditions:
CPU operation speed (fSYS) : 60 MHz
I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz)
I2S data transfer bit length : 16 bits
DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S
Calculation example:
DMAC source data read time:
Internal RAM data read time = 1 state/4 bytes (However, the first 1 byte requires 2 states.)
DMAC destination write time:
I2S register write time = 2 states/4 bytes
Transfer count
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as follows:
5 Kbytes/4 bytes = 1280 [times]
Since I2S generates an interrupt for every 64 bytes, the DMAC’s counter A is set to 16 (64 bytes/4 bytes = 16
times) and counter B is set to 80.
* Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state)
occurs 80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead
time of 2 states is also needed for each interrupt request, requiring additional 160 states in total.
tSTOP (HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / fSYS [S] = 68 [μS]
HDMA start interval [s] = 1 / I2S sampling frequency [Hz] × (64 / 16 )
= 83.33 [mS]
CPU bus stop rate = tSTOP (HDMA) [s] / HDMA start interval [s]
= 68 [μS] / 83.33 [mS] = 0.08 [%]