TMP92CZ26A

92CZ26A-629

3.26.1.2 Data Registers

The data registers are arranged as shown below.

Data Registers

Bits<63:56> Bits<55:48> Bits<47:40> Bits<39:32> Bits<31:24> Bits<23:16> Bits<15:8> Bits<7:0>
Multiplier A
Register
(1BE3H)
(1BE2H)
(1BE1H)
MACMA
(1BE0H)
Multiplier B
Register
(1BE7H)
(1BE6H)
(1BE5H)
MACMB
(1BE4H)
MAC
Register
(1BEFH)
(1BEEH)
(1BEDH)
MACORH
(1BECH)
(1BEBH)
(1BEAH)
(1BE9H)
MACORL
(1BE8H)
Note 1: After reset, all the registers are cleared to “0”.
Note 2: Read-modify-write instructions can be used on all the registers.
Note 3: All the registers can be accessed in long word, word, or byte units.
Note 4: When MACCR<MSTTG2:0> is set to “0”, “001”, “010” or “01 1” and the registers are written in word or byte units, the
<7:0> bits of each register must be written last.
Note 5: The MACORL register is fixed one system clock (fSYS) af ter calculation is started, and the MACORH register is fixed
two system clocks (fSYS) after calculation is started. Therefore, to read the MACOR register immediately after
calculation, be sure to read the MACORL register first.