TMP92CZ26A

92CZ26A-298

(3) Timer registers (TB0RG0H/L, TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the
up counter UC10 matches the value set in this timer register, the comparator match
detect signal will go active.
Setting data for both upper and lower timer registers is need ed. F or exam ple, using
2-byte data transfer instruction or using 1-byte data transfer instruction twice for
lower 8 bits and upper 8 bits in order.
(The compare circuit will not operate if only the lower 8 bits are written. Be sure to
write to both timer registers (16 bits) from the lower 8 bits followed by the upper 8
bits.)
The TB0RG0H/L timer register has a double-buffer structure, which is paired with
register buffer 10. The value set in TB0RUN<TB0RDE> determines whether the
double-buffer structure is enabled or disabled: it is disabled when <TB0RDE> = “0”,
and enabled when <TB0 RDE> = “1”.
When the double buffer is enabled, data is transferr ed from the register bu ffer 10 to
the timer register when the values in the up counter (UC10) and the timer register
TB0RG1H/L match.
The double buffer circuit incorporates two flags to indicate whether or not data is
written to the lower 8 bits and the upper 8 bits of the register buffer, respectively.
Only when both flags are set can data be transferred from the register buffer to the
timer register by a match between the up-counter UC10 and the timer register
TB0RG1. This data transfer is performed so long as 16-bit data is written in the
register buffer regardless of the register buffer to the timer register unexpectedly as
explained below.
For example, let us assume tha t an int errupt occurs when on ly t he low er 8 bi ts (L1)
of the register buffer data (H1L1) have been written and the interrupt routine
includes writes to all 16 bits in the register buffer and a transfer of the data to the
timer register. In this case, if the higher 8 bits (H1) are written after the interrupt
routine is completed, only the flag for the higher 8 bits will be set, the flag for the
lower 8 bits having been cleared in the interrupt routine. Therefore, even if a match
occurs between UC10 and TB0RG1, no data transfer will be performed.
Then, in an attempt to set the next set of data (H2L2) in the register buffer, when
the lower 8 bits (L2) are written, this will cause the flag for the lower 8 bits to be set as
well as the flag for the higher 8 bits which has been set by writing the previous data
(H1). If a match between UC10 and TB0RG1 occurs before the higher 8 bits (H2) are
written, this will cause unexpected data (H1L2) to be sent to the timer register instead
of the intend ed data (H2L2).
To avoid such transfer timing problems due to interrupts, the DI instruction
(disable interrupts) and the EI (enable interrupts) can be executed before and after
setting data in the register buffer, respectively.
After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to
be used after a reset, data should be written to it beforehand.
On a reset <TB0RDE> is initialized to “0”, disabling the double buffer. To use the
double buffer, write data to the timer register, set <TB0RDE> to “1”, then write data
to the register buffer 10 as shown below.