Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG 3.13.2 Operation

TMP92CZ26A
92CZ26A-297
3.13.2 Operation
(1) Prescaler
The 5-bit prescaler generates the source cloc k for TMRB0. The prescaler clock (φT0)
is selected by the register SYSCR0<PRCK> of clock gear. This prescaler can be
started or stopped using TB0RUN<TB0RUN>. Counting starts when <TB0RUN> is
set to “1”; the prescaler is cleared to “0” and stops operation when <TB0RUN> is
cleared to “0”.
The resolutio n of prescaler is showed in the Table 3.13.2.
Table 3.13.2 Prescaler Clo ck Resolution
Timer counter input clock
Prescaler of TMRB
TBxMOD<TBxCLK1:0>
Clock gear
selection
SYSCR1
<GEAR2:0>
Prescaler of
clock gear
SYSCR0
<PRCK>
−
φT1(1/2) φT4(1/8) φT16(1/32)
1/1 fc/8 fc/32 fc/128
1/2 fc/16 fc/64 fc/256
1/4 fc/32 fc/128 fc/512
1/8 fc/64 fc/256 fc/1024
1/16
1/2
fc/128 fc/512 fc/2048
1/1 fc/32 fc/128 fc/512
1/2 fc/64 fc/256 fc/1024
1/4 fc/128 fc/512 fc/2048
1/8 fc/256 fc/1024 fc/4096
fc
1/16
1/8
1/2
fc/512 fc/2048 fc/8192
(2) Up counter (UC10)
UC10 is a 16-bit binary counter which counts up pulses input from the clock
specified by TB0MOD<TB0CLK1:0>.
Any one of the prescaler internal clocks φT1, φTB0 and φT16 or an external clock
input via the TB0IN0 pin can be selected as the input clock. Cou nting or stop ping and
clearing of the counter is controlled by TB0RUN<TB0RUN>.
When clearing is enabled, the up counter UC10 will be cleared to zero each time its
value match es the value in the tim er register TB0 RG1H/L. Clea ring can be enabled or
disabled using TB0MOD<TB0CLE>.
If clearing is disabled, the counter operates as a free running counter.