TMP92CZ26A

92CZ26A-361

Example: In case receive data N times
INTSBI interrupt (After transmitting data)
7 6 5 4 3 2 1 0
SBICR1 ← X X X X X X X X Set the bit number of receive data and ACK.
Reg. ← SBIDBR Load the dummy data.
End of interrupt
INTSBI interrupt (Receive data of 1st to (N−2) th)
7 6 5 4 3 2 1 0
Reg. ← SBIDBR Load the data of 1st to (N−2)th.
End of interrupt
INTSBI interrupt ((N−1) th Receive data)
7 6 5 4 3 2 1 0
SBICR1 ← X X X 0 0 X X X Not generate acknowledge signal
Reg. ← SBIDBR Load the data of (N−1)th
End of interrupt
INTSBI interrupt (Nth Receive data)
7 6 5 4 3 2 1 0
SBICR1 ← 0 0 1 0 0 X X X Generate the clock for 1bit transmit
Reg. ← SBIDBR Receive the data of Nth.
End of interrupt
INTSBI interrupt (After receiving data)
The process of generating stop condition Finish the transmit of data
End of interrupt
Note: X: Don’t care