TMP92CZ26A
92CZ26A-289
In this mode a programmable square wave is generated by inverting the timer
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
The value set in TA0RE G must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
TA01RUN<TA1RUN> should be set to 1 so that UC 1 is set for counting.
Figure 3.12.21 shows a block diagram representing this mode.
Figure 3.12.21 Block Diagram of 8-Bit PPG Output Mode
If the TA0REG doub le buffer is enabled in this mode, the value of the register buffer
will be shifted into TA0R EG e ach time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is
varied).
Figure 3.12.22 Operation of Register Buffer
Note: The values that can be set in TAxREG renge from 01h to 00h (equivalent to 100h). If the maximum value 00h
is set , the match-detect signal goes active when the up-counter overfolws.
8-bit
up counter
(UC0)
Comparator Comparator
TA0IN
φT1
φT4
φ
T16
TA01MOD<TA0CLK1:0>
TA1FF
TA0REG
Register buffer TA1REG
TA01RUN<TA0RDE>
TA0REG-WR
TA01RUN<TA0RUN> TA1OUT
TA1FFCR<TA1FFIE>
INTTA0
INTTA1
Shift trigge
r
Internal data bus
Selecto
r
Inversion
Selecto
r
Q2 Q1
Match with TA0REG
and up counte
r
Match with TA1REG
Q3 Q2
(Up counter
=
Q1) (Up counter
=
Q2)
Shift from register buffer
TA0REG (Register buffer)
write
TA0REG
(Value to be compared)
Register buffe
r