Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-304

TMP92CZ26A
92CZ26A-304
TMRB1 Mode Register
7 6 5 4 3 2 1 0
Bit symbol − − TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0
Read/Write R/W W* R/W
After Reset 0 0 1 0 0 0 0 0
Function Always write “0”. Software
capture control
0: Execute
1: Undefined
Capture timing
00:Disable
INT7 occurs at
rising edge
01:TB1IN0 ↑
INT7 occurs at
rising edge
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at
falling edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
Control
Up counter
0:Disable
1: Enable
TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
Control clearing for up counter (UC12)
0 Disable
<TB1CLE> 1 Enable clearing by match with
TB1RG1H/L
Figure 3.13.5 Register for TMRB (3 )
TMRB1 source clock
00 TB1IN0 pin input
01 φT1
10 φT4
<TB1CLK1:0>
11 φT16
Capture/interrupt timing
Capture control INT7 control
00 Disable
01 Capture to TB1CP0H/L at rising edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0
10 Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at falling edge of TB1IN0 INT7 occurs at the rising
edge of TB1IN0
<TB1CPM1:0>
11 Capture to TB1CP0H/L at rising edge of TA3OUT
Capture to TB1CP1H/L at falling edge of TA3OUT INT7 occurs at the rising
edge of TB1IN0
Software capture
0 The value of up counter is captured to TB1CP0H/L
<TB1CP0I> 1 Undefined (Note)
TB1MOD
(1192H)
Prohibit
read-
modify-
write