TMP92CZ26A
92CZ26A-334
b. Receiving
In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the
data is shifted to Receiving Buffer 1. This is initiated when th e Receive Interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received,
the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown
below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt to be
generated.
Setting SC0MOD0<RXE> to 1 initiates SCLK0 output.
Figure 3.14.15 Receiving operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input Mode the data is shifted to R eceiving Bu ffer 1 when th e SCLK inpu t
goes active. The SCLK input goes active when the Receive Interrupt flag INTES0
<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data
is shifted to Receiving Buffer 2 (SC0BUF) following the timing shown below and
INTES0 <IRX0C> is set to 1 again, causing an INTRX0 interr upt to be generated.
Figure 3.14.16 Receiving Operation in I / O interface Mode (SCLK0 Input Mode)
Note: The system must be put in the Receive Enable state (SC0MOD0<RXE> = 1) before data can be received.
SCLK0 output
(<SCLKS> = 0:
risin
g
ed
g
e mode
)
IRX0C
(INTRX0 interrupt
request)
RXD0 Bit0 Bit1 Bit6
Bit7
SCLK0 output
(<SCLKS> = 1:
fallin
g
ed
g
e mode
)
SCLK0 input
(<SCLKS> =0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
IRX0C
(INTRX0 interrupt request)
RXD1 Bit1 Bit6 Bit7 Bit5
B
it