TMP92CZ26A

92CZ26A-69

3.5.1 General-purpose Interrupt Processing

When the CPU accepts an interrupt, it usually performs the following sequence of
operations. However, in the case of s oftware interrupts and illegal instruction interrupts
generated by the CPU, the CPU skips steps (1) and (3), and exec utes only steps (2), (4), and
(5).
(1) The CPU reads the interrupt vect or from the interr upt controlle r. When more than on e
interrupt with the same priority level have been generated simultaneously, the
interrupt controller generates an interrupt vector in accordance with the default
priority and clears the interrupt requests. (The default priority is determined as
follows: The sm aller the vector value, the higher the pri ori ty.)
(2) The CPU pushes the pr ogram count er (PC ) and status regist er ( SR) on to the top o f the
stack (Pointed to by XSP).
(3) The CPU sets the value of the CPU’s interrupt mask register <IFF2:0> to the priority
level for the accepted interrupt plus 1. However, if the priority level for the accepted
interrupt is 7, the register’s value is set to 7.
(4) The CPU increm ents the interrupt nes ting counter INTNEST by 1.
(5) The CPU jumps to the address given by adding the contents of address FFFF00H + the
interrupt vector, then starts the interrupt processi ng routine.
On completion of interrupt processing, the RETI instruction is used to return control
to the main routine. RETI restores the contents of the program counter and the status
register from the stack an d decrements the interrupt nesting co unter INT NEST by 1.
Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts,
however, can be enabled or disabled by a user program. A program can set the priority
level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt
request.) If an interrupt request is rec eived for an interru pt with a prior ity level equal to
or greater than the value set in the CPU interr upt mask register <IFF2:0>, the CPU will
accept the interrupt. The CPU interrupt mask register <IFF2:0> is then set to the value
of the priority le vel for the accepted in terrupt plus 1.
If during interrupt processing, an interrupt is generated with a higher priority than the
interrupt currently b eing processed, or if, during the processin g of a non-maskable
interrupt processing, a non-maskable interrupt request is g enerated from anoth er source,
the CPU will suspend the rout ine which it is currently executing and accept the ne w
interrupt. When processing of the new interrupt has been completed, the CPU will resume
processing of the suspen ded interrupt.
If the CPU receiv es another i nterrupt request wh ile p erformin g processin g steps (1) to
(5), the new interrupt will be sampled immediately after execution of the first instruction
of its interru pt processing routin e. Specifying DI as the start inst ruction disables nesting
of maskable interrupts.
After a reset, initial izes the interrupt mask register <IFF2:0> to 111, disabling all
maskable interrupts.
Table 3.5.1 shows the TMP92CZ26A interrupt vectors and micro DMA start vectors.
FFFF00H to FFFFFFH (256 bytes) is designated as the interru pt vector area.