TMP92CZ26A

92CZ26A-67

3.5 Interrupts

Interrupts are controlled by the CPU Interrupt Mask Register <IFF2 to 0> (bits 12 to 14
of the Status Regist er) and by the built-in interrupt controller.
TMP92CZ26A has a total of 56 interru pts divided into the followin g five types:
Interrupts generated by CPU: 9 sources
• Software interrupts: 8 sources
• Illegal Instruction interrupt: 1 source
Internal interrupts: 38 sources
• Internal I/O interrupts: 30 sources
• Micro DMA Transfer End interrupts /HDMA Transfer End interrupts: 6 sources
• Micro DMA Transfer En d interrupts: 2 source
External interrupts: 9 sources
• Interrupts on external pins (INT0 to INT7, INTKEY)
A fixed individual interrupt vector number is assigned to each interrupt source. Any one of
seven levels of priority can also be assigned to each maskable interrupt. Non-maskable
interrupts have a fixed priority level of 7, the highest lev el.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
to the CPU. When more than one interrupt are generated simultaneously, the interrupt
controller sends the priority value of the interrupt with the highest priority to the CPU. (The
highest priority le vel is 7, the level used for non-maskable interrupts.)
The CPU compares the interrupt priority level which it receives with the value held in the
CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is greater than or
equal to the value in the interrupt mask register, the CPU acce pts the interrupt.
However, software interrupts and illegal instruction interrupts generated by the CPU, and
are processed irresp ective of the value in <IFF 2: 0>.
The value in the in terrupt mask register <IFF2:0> can be changed using the EI instruction
(EI num sets <IFF2:0> to num). F or example, the command EI3 enables the acceptance of all
non-maskable interrupts and of maskable interrupts whose priority level, as set in the
interrupt controller, is 3 or higher. The commands EI and EI0 enable the acceptance of a ll
non-maskable interrupts and of maskable int errupts with a priority level of 1 or above (hence
both are equivalent to the command EI1).
The DI instruction (Sets <IF F 2: 0> to 7) is exactly equivalent to the EI7 instruction. Th e DI
instruction is used to disabl e all maskable interrupts (since the priority level for maska ble
interrupts ranges from 0 t o 6). The EI instruction takes effect as soon as i t is executed.
In addition to the g eneral-purpose interrupt processing mode described above, there is also a
micro DMA processing mode that can transfer data to internal/external m emory and built-in
I/O, and HDMA processing mode. In micro DMA mode the CPU, and in HDMA mode the DMA
controller autom atically transfers data in 1b yte, 2byte or 4byte blocks. HDMA mode allows
transfer faster than Micro DM A mode.
In addition, the TMP92CZ26A also has a software start function in which micr o DMA and
HDMA processing is requested in software rather than by an interrupt. Figure 3.5.1 is a
flowchart showing overall interrupts processing.