TMP92CZ26A

92CZ26A-405

3.16.3.25 EPx_SINGLE Register
This register sets mode of FIFO in each endpoint (SINGLE/DUAL).
7 6 5 4 3 2 1 0
bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_SINGLE EP2_SINGLE EP1_SINGLE
Read/Write R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0
Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A.
Bit number
0: No use
1: EP1_SINGLE
2: EP2_SINGLE
3: EP3_SINGLE
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
When EPx_SELECT bit is “1”, EPx_SINGLE bit become valid in following content.
0: DUAL mode 1: SINGLE mode
If set ting content of EPx_SINGLE bit to valid, set EPx_SELECT bit to “1”.
0: Invalid 1: Valid
3.16.3.26 EPx_BCS Register
This register set mode that access to FIFO in each endpoint.
7 6 5 4 3 2 1 0
bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_BCS EP2_BCS EP1_BCS
Read/Write R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0
Bit number
0: No use
1: EP1_BCS
2: EP2_BCS
3: EP3_BCS
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
Always write “1” to EPx_BCS bit.
0: Reserved 1: CPU access
If setting content of EPx_BCS bit to valid, set EPx_SELECT bit to “1”.
0: Invalid 1: Valid
EPx_SINGLE1
(07D1H)
EPx_BCS1
(07D3H)