TMP92CZ26A

92CZ26A-190

CPU Data
Operand Data
Size (bit)
Operand Start
Address
Bus width of Mem ory
(bit ) CPU Addres s D31 to D24 D23 to D16 D15 to D8 D7 to D0
4n + 0 8/16/32 4n + 0 xxxxx xxxxx xxxxx b7 to b0
8 4n
+ 1 xxxxx xxxxx xxxxx b7 to b0
4n + 1 16/32 4n
+ 1 xxxxx xxxxx b7 to b 0 xxxxx
8/16 4n
+ 2 xxxxx xxxxx xxxxx b7 to b0
4n + 2 32 4n
+ 2 xxxxx b7 to b0 xxxxx xxxxx
8 4n
+ 3 xxxxx xxxxx xxxxx b7 to b0
16 4n
+ 3 xxxxx xxxxx b7 to b 0 xxxxx
8
4n + 3
32 4n
+ 3 b7 to b0 xxxxx xxxx x xxxxx
(1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0
8 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8
4n + 0
16/32 4n
+ 0 xxxxx xxxxx b15 to b8 b7 to b0
(1) 4n + 1 xxxxx xxxxx xxxxx b7 to b0
8 (2) 4n + 2 xxxxx xxxxx xxxxx b15 to b8
(1) 4n + 1 xxxxx xxxxx b7 to b 0 xxxxx
16 (2) 4n + 2 xxxxx xxxxx xxxxx b15 to b8
4n + 1
32 4n
+ 1 xxxxx b15 to b8 b7 to b0 xxxxx
(1) 4n + 2 xxxxx xxxxx xxxxx b7 to b0
8 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8
16 4n
+ 2 xxxxx xxxxx b15 to b8 b7 to b0
4n + 2
32 4n
+ 2 b15 to b8 b7 to b0 xxxxx xxxxx
(1) 4n + 3 xxxxx xxxxx xxxxx b7 to b0
8 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8
(1) 4n + 3 xxxxx xxxxx b7 to b 0 xxxxx
16 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8
(1) 4n + 3 b7 to b0 xxxxx xxxx x xxxxx
16
4n + 3
32 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8
(1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0
(2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8
(3) 4n + 2 xxxxx xxxxx xxxxx b23 to b16
8
(4) 4n + 3 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 0 xxxxx xxxxx b15 to b8 b7 to b0
16 (2) 4n + 2 xxxxx xxxxx b31 to b24 b23 to b16
4n + 0
32 4n
+ 0 b31 to b24 b23 to b16 b15 to b8 b7 to b0
(1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0
(2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8
(3) 4n + 2 xxxxx xxxxx xxxxx b23 to b16
8
(4) 4n + 3 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 1 xxxxx xxxxx b7 to b 0 xxxxx
(2) 4n + 2 xxxxx xxxxx b23 to b16 b15 to b8
16
(3) 4n + 4 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 1 b23 to b16 b15 to b8 b7 to b0 xxxxx
4n + 1
32 (2) 4n + 4 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 2 xxxxx xxxxx xxxxx b7 to b0
(2) 4n + 3 xxxxx xxxxx xxxxx b15 to b8
(3) 4n + 4 xxxxx xxxxx xxxxx b23 to b16
8
(4) 4n + 5 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 2 xxxxx xxxxx b15 to b8 b7 to b0
16 (2) 4n + 4 xxxxx xxxxx b31 to b24 b23 to b16
(1) 4n + 2 b15 to b8 b7 to b0 xxxxx xxxxx
4n + 2
32 (2) 4n + 4 xxxxx xxxxx b31 to b24 b23 to b16
(1) 4n + 3 xxxxx xxxxx xxxxx b7 to b0
(2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8
(3) 4n + 5 xxxxx xxxxx xxxxx b23 to b16
8
(4) 4n + 6 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 3 xxxxx xxxxx b7 to b 0 xxxxx
(2) 4n + 4 xxxxx xxxxx b23 to b16 b15 to b8
16
(3) 4n + 6 xxxxx xxxxx xxxxx b31 to b24
(1) 4n + 3 b7 to b0 xxxxx xxxx x xxxxx
32
4n + 3
32 (2) 4n + 4 xxxxx b31 to b24 b23 to b16 b15 to b8

xxxxx: During read, input data to the bus is ignored. At write, the bus is high impedance and the write

strobe signal remai ns no-active.