TMP92CZ26A

92CZ26A-525

• Setting method
The front dummy LHSYNC (vertical front porch) not accompanied by valid data in
the total of LHSYNC period in the LVSYNC period is defined by the value set in
LCDPRVSP<PLV6:0>.
Front dummy LHSYNC (vertical front porch) = <PLV6:0>
The back dummy LHSYNC (vertical back porch) is define d as fo llows:
(<LVP9:0> + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC:
<PLV6:0>)
The vertical back porch must have a minimum of one dummy clock.
The front dummy LCP0 (horizontal front porch) not accompanied by valid data in the
total number of LCP0 clocks in the LHSYNC period is defined by the value set in
LCDLDDLY<LDD6:0>.
Front dummy LCP0 (horizontal front porch) = <LDD6:0>
The back dummy LCP0 (horizontal back porch) is defined as follows:
(<LH15:0> + 1) − (valid LCP0: segment size) − (front dummy LCP0: <LDD6:0>)
Note 1: The back dummy LCP0 (horizontal back porch) must have a minimum of two LCP0 clocks.
Note 2: The delay time that is set in LCDLDDLY<LDD6:0> is counted based on LHSYNC (with 0 delay).
7 6 5 4 3 2 1 0
bit Symbol PDT LDD6 LDD5 LDD4 LDD3 LDD2 LDD1 LDD0
Read/Write R/W W
After reset 0 0 0 0 0 0 0 0
Function
Data output
timing
0: Sync with
LLOAD
1: 1 clock later
than LLOAD
LLOAD delay (bits 6-0)
Example 1) Setting the refresh rate to 200 Hz under the following conditions:
fSYS = 30 MHz, STN mode, 320-segment × 240-common, 4096-color display,
LCDMODE0<SCPW1:0> = 00
Internal reference clock LCP0 = fSYS / 4 = 30 [MHz] / 4 = 7.5 [MHz]
Therefore, LCP0 period = 1 / 7.5 [MHz] = 0.133 [μS]
Condition 1: Refresh rate = 200 Hz, Refresh cycle = 5 [ms
Condition 2: LH = <LH15:0> ≥ (320×3/8) − 1 = 119
Condition 3: LV = <LVP9:0> ≥ 240 − 1
When <LVP9:0> = 239 (minimum value):
LVSYNC [s: period] = LHSYNC [s: period] × (<LVP9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LVP9:0> + 1)
5 [ms] = (1 / 7.5 [MHz]) × (LH + 1) ×240
LH + 1 = (5 × 10 -3) × (7.5 × 10 6) / 240
= 156.25
LCDLDDLY
(
0290H
)