TMP92CZ26A
92CZ26A-89
3.6.1 Block Diagram
Figure 3.6.1 shows an overall block diagram for the DMAC.
Note: “n” denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5).
Figure 3.6.1 Overall Block Diagram
DMAnV
DMAR
DMAC or micro DMA request
source setting
DMAC or micro DMA soft start
setting
DMAB
Micro DMA burst setting
DMASEL
DMAC or micro DMA select
setting
INTC (Interrupt Controller)
Interrupt REQ
DMASn
Micro DMA source address setting
31 0
7 0
DMADn
Micro DMA destination address setting
DMACn
Micro DMA transfer count setting
15 0
DMAMn
Micro DMA mode setting
7 0
CPU
HDMASn
DMA source address setting
31 0
HDMADn
DMA destination address setting
HDMACAn
DMA transfer count A setting
1
5
0
HDMAMn
DMA mode setting
7 0
DMAC
HDMACBn
DMA transfer count B setting
HDMAE
DMA operation enab l e/di sable
Micro DMA REQ,
Micro DMA Channel
Micro DMA ACK,
INTTCn
Bus REQ
Bus ACK
DMA REQ,
DMA Channel
DMA ACK,
INTDMAn
Bus REQ
Bus ACK
LCD Controller
A
ddress Bus
Data Bus
State
A
ddress Bus
Data Bus
State
A
ddress Bus
Data Bus
State
A
ddress Bus
Data Bus
State
Source Memory, I/O
Destination Memory, I/O
Bus
Multiplexer
HDMATR
DMA maximum bus occupancy
time setting, mode setting
SDRAM Controller
Bus ACK
Bus REQ
State
A
ddress Bus
A
ddress Bus
Data Bus
State