TMP92CZ26A

92CZ26A-88

3.6 DMAC (DMA Controller)

The TMP92CZ26A incorporates a DMA controller (DMAC) havin g six channels. This D MAC can
realize data transfer fast er than the micro DMA function by the 900/H1 CPU .
The DMAC has the following features:
1) Six independ ent channels of DMA
2) Two types of transfer start requests
Hardware request (using an interrupt source connected with the INTC) or software
request can be selected for each chann el.
3) Various source/destination combinations
The combination of transfer source and destination can be selected for each channel
from the following four types: me mory to memory, memory to I/O, I/O to memory, I/O
to I/O.
4) Transfer address mode
Only the dual address mode is support ed.
5) Dual-count mechanism and DMA end interrupt
Two count registers are provided to execute multiple DMA transfers by one DMA
request and to generate multiple DMA requests at a time. The DMA end interrupt
(INTDMA0 to INTDMA5 ) is also provided so that a general- purpose interrupt routine
can be used to prepar e for the next processin g.
6) Priorities among DM A channe ls (th e sam e as th e micro DMA accept ance specific ations
of the INTC)
DMA requests are basic ally acc epted in the ord er in which th ey are asserted . If more
than one request is asserted simultaneously or it looks as if two requests were
asserted simultan eously because one of the reques ts has been put on hold while other
processing was being performed, the smaller-numbered channel is given a higher
priority.
7) DMAC bus occupancy limiting functi on
The DMAC incorporates a special timer for limiting its bus occupancy time to avoid
excessive interf erence with the CPU or LCDC operation.
8) The DMAC can be used in HALT (IDLE2) mode.