TMP92CZ26A

92CZ26A-90

3.6.2 SFRs

The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit

data bus.

(1) HDMASn (DMA Transfer Source Address Setting Register)

The HDMASn register is used to set the DMA transfer source address. When the source

address is updated by DMA execution, HDMASn is also updated.

HDMAS0 to HDMAS5 have the same configuration.

Although the bus sizing function is supported, the address alignment function is not

supported. Therefore, specify an even-numbered address for transferring 2 bytes and an

address that is an integral multiple of 4 for transferring 4 bytes.

HDMASn Register

7 6 5 4 3 2 1 0

bit Symbol DnSA7 DnSA6 DnSA5 DnSA4 DnSA3 DnSA2 DnSA1 DnSA0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Source address [7:0] for DMAn

15 14 13 12 11 10 9 8

bit Symbol DnSA15 DnSA14 DnSA13 DnSA12 DnSA11 DnSA10 DnSA9 DnSA8
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Source address [15:8] for DMAn

23 22 21 20 19 18 17 16

bit Symbol DnSA23 DnSA22 DnSA21 DnSA20 DnSA19 DnSA18 DnSA17 DnSA16
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Source address [23:16] for DMAn

Source address
[23:16]
Source address
[15:8]
Source address
[7:0]
Channel 0
(0902H)
(0901H)
HDMAS0
(0900H)
Channel 1
(0912H)
(0911H)
HDMAS1
(0910H)
Channel 2
(0922H)
(0921H)
HDMAS2
(0920H)
Channel 3
(0932H)
(0931H)
HDMAS3
(0930H)
Channel 4
(0942H)
(0941H)
HDMAS4
(0940H)
Channel 5
(0952H)
(0951H)
HDMAS5
(0950H)
Note: Read-modify-write instructions can be used on all these registers.

Figure 3.6.2 HDMASn Register

HDMASn