Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG TMP92CZ26A , 92CZ26A-169, 3.7.21 Port V (PV0 to PV4, PV6, PV7)

TMP92CZ26A
92CZ26A-169
3.7.21 Port V (PV0 to PV4, PV6, PV7)
Port V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set
individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and
output latch to “0”. In add ition to funct ioning as gen eral-purpose I/O port pins, PV can also
function as input or output pin for SBI (SDA, SCL) and output for SIO(SCLK0) (Note).
Above settin g is used the control register PVCR and functi on register PVFC.
Port V3 and V4 are 2 -bit general- purpose output ports. Resettin g clear port V3 and V4 to
output latch to “0”.
Note: SIO function support function that input clock from SCLK0, basically. However, if setting to PV0 pin, this function supports only
the output function.
Figure 3.7.57 Port V0 to V2
PV0 (SCLK0)
PV1
PV2
Internal data bus
Direction control
(on bit basis)
Reset
PVCR write
PV write
Function control
(on bit basis)
PVFC write
R
Output latch
SCLK0
Selector
A
B
S
Selector
A
B
PV read