TMP92CZ26A

92CZ26A-353

(6) Transmitter/Receiv er sel ection
Set the SBICR2<TRX> to “1” for operating the TMP92CZ26A as a transmitter.
Clear the <TRX> to “0” for operation as a receiver.
In Slave Mode,
z Data with an addressing format is transferred
z A slave address with the same value that an I2CAR
z A GENERAL CALL is received (all 8-bit data are “0” after a start condition)
The <TRX> is set to “1” by the hardware if the direction bit ( WR/ ) sent from the
master device is “1”, and is cleared to “0” by the har dware if the bit is “0”.
In the Master Mode, aft er an Acknowledge signa l is returned from the slave device,
the <TRX> is cleared to “0” by the hard ware if a transmitted direction bit is “1”, and is
set to “1” by th e hardware if it is “0”. When an Ac knowledge si gnal is not ret urned, the
current condition is maintained.
The <TRX> is cleared to “0” by the hardware after a stop condition on the I2C bus is
detected or arbitra tion is lost.
(7) Start/Stop condition generation
When the SBISR<BB> is “0”, slave address and direction bit which are set to
SBIDBR are output on a bus after generating a start condition by writing “1” to the
SBICR2 <MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data
buffer register (SBIDBR) and set “1” to <ACK> b eforehand.
Figure 3.15.10 Start condition generation and slave address generation
When the <BB> is “1”, a sequence of generating a stop condition is started by
writing “1” to the <MST, TRX, PIN>, and “0” to the <BB>. Do not modify the contents
of <MST, TRX, BB, PIN> until a stop condition is generated on a bus.
Figure 3.15.11 Stop condition generation
The state of the bus can be ascertained by reading the contents of SBISR<BB>.
SBISR<BB> will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.
SCL pin
Start condition
A6
Slave address and the direction bit
A
cknowledge
signal
1
SDA pin
234567 8 9
A5 A4 A3 A2 A1 A0 R/ W
Stop condition
SCL pin
SDA pin