Toshiba H1 Series, TLCS-900, TMP92CZ26AXBG 3.8 Memory Controller (MEMC) 3.8.1 Functions

TMP92CZ26A
92CZ26A-180
3.8 Memory Controller (MEMC)
3.8.1 Functions
TMP92CZ26A has a memory controller with a variable 4-block address area that controls as
follows.
(1) 4-block address area support
Specifies a start address and a block size for 4-block address area (block0 to 3).
* SRAM or ROM : All CS-blocks (CS0 to CS3) are supported.
* SDRAM : Either CS1 or CS2-blocks is supported.
* Page-ROM : Only CS2-blocks is support ed.
* NAND-Flash : CS setting is not needed. If using NAND-Flash, set
BROMCR<CSDIS> to “1” as external area for avoiding
conflicting with other CS memory.
(2) Connecting memory specifications
Specifies SRAM, ROM, SDRAM as memories to connect with the selected address areas.
(3) Data bus width selection
Whether 8-bit or 16bit is selected as the data bus width of the r espective block address areas.
(4) Wait control
Wait specification bit in the control reg ister and WAIT input pin control t he number of wait s
in the external bus cycle. The number of waits of read cycle and write cycle can be specified
individually. The number of waits is contro lled in 15 mode mentioned below.
0 to 10 wait, 12wait,
16 wait, 20 wait
4+N wait (controls with WAIT pin)