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Intel 845 Manual

148 pages1.09 Mb

Intel 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR
3Contents
- 7Figures
- Tables
8Revision History
9Intel 82845 MCH Features
- 10
- 10 Intel 82845 MCH for SDR Datasheet
- System Block Diagram
111 Introduction
- 1.1 Terminology and Notations
- 131.2 Reference Documents
- 141.3 Intel 845 Chipset System Architecture
  - Intel 82801BA I/O Controller Hub 2 (ICH2)
- 1.4 Intel 82845 MCH Overview
  - 151.4.1 System Bus Interface
  - 1.4.2 System Bus Error Checking
  - 161.4.3 System Memory Interface
  - 1.4.4 AGP Interface
  - 171.4.5 Hub Interface
  - 1.4.6 Intel MCH Clocking
  - 181.4.7 System Interrupts
  - 1.4.8 Powerdown Flow
192 Signal Description
- 20Signal Description
- 20 Intel 82845 MCH for SDR Datasheet
- Figure 1. Intel MCH Simplified Block Diagram
- 212.1 System Bus Signals
- 232.2 SDR SDRAM Interface Signals
- 2.3 Hub Interface Signals
- 242.4 AGP Interface Signals
  - 2.4.1 AGP Addressing Signals
  - 252.4.2 AGP Flow Control Signal s
  - 2.4.3 AGP Status Signals
    - Signal Description
    - 26 Intel 82845 MCH for SDR Datasheet
  - 262.4.4 AGP Strobes Signals
  - 2.4.5 AGP/PCI Signals
- 282.5 Clocks, Reset, and Miscellaneous Signals
- 292.6 Voltage Reference and Power Signals
  - Signal Description
  - 30 Intel 82845 MCH for SDR Datasheet
- 302.7 Reset States During Reset
313 Register Description
- 3.1 Register Terminology
- 323.2 PCI Bus Configuration Space Access
  - 333.2.1 Standard PCI Bus Configuration Mechanism
  - 3.2.2 Routing Configuration Accesses
    - PCI Bus 0 Configuration Mechanism
    - Primary PCI and Downstream Configuration Mechanism
    - AGP Configuration Mechanism
- 343.3 I/O Mapped Registers
  - 3.3.1 CONF_ADDRConfiguration Address Register
  - 3.3.2 CONF_DATAConfiguration Data Register
- 363.4 Memory-Mapped Register Space
  - 373.4.1 DRAMWIDTHDRAM Width Register
  - 383.4.2 DQCMDSTRStrength Control Register (SDQ and CMD Signal Groups)
  - 393.4.3 CKESTRStrength Control Register (SCKE Signal Group)
  - 403.4.4 CSBSTRStrength Control Register (SCS# Si gnal Group)
  - 413.4.5 CKSTRStrength Control Register (Cl ock Si gnal Group)
  - 423.4.6 RCVENSTRStrength Control Register (RCVENOUT Signal Group)
    - Register Description
    - Intel 82845 MCH for SDR Datasheet 43
- 433.5 Host-Hub Interface Bridge Device Registers (Device 0)
  - 453.5.1 VIDVendor Identificati on Regi ster (Device 0)
  - 3.5.2 DIDDevice Identification Register (Device 0)
  - 463.5.3 PCICMDPCI Command Register (Device 0)
  - 473.5.4 PCISTSPCI Status Register (Device 0)
  - 483.5.5 RIDRevision Identification Register (Device 0)
  - 3.5.6 SUBCSub-Class Code Register (Device 0)
  - 3.5.7 BCCBase Class Code Register (Device 0)
  - 493.5.8 MLTMaster Latency Timer Register (Device 0)
  - 3.5.9 HDRHeader Type Register (Device 0)
  - 503.5.10 APBASEAperture Base Configuration Register (Device 0)
  - 513.5.11 SVIDSubsystem Vendor Identification (Device 0)
  - 3.5.12 SIDSubsystem Identification (Device 0)
  - 3.5.13 CAPPTRCapabilities Pointer (Device 0)
  - 523.5.14 AGPMAGP Miscellaneous Configurati on Regi ster (Device 0)
  - 3.5.15 DRB[0:7]DRAM Row Boundary Registers (Device 0)
  - 533.5.16 DRADRAM Row Attribute Registers (Device 0)
  - 553.5.17 DRTDRAM Timing Register (Device 0)
  - 563.5.18 DRCDRAM Controller Mode Register (Device 0)
  - 583.5.19 DERRSYNDRAM Error Syndrome Register (Device 0)
  - 3.5.20 EAPError Address Pointer Register (Device 0)
  - 593.5.21 PAM[0:6]Programmable Attribute Map Registers (Device 0)
    - 61DOS Application Area (00000h9FFFh)
    - Video Buffer Area (A0000hBFFFFh)
    - Expansion Area (C0000hDFFFFh)
    - Extended System BIOS Area (E0000hEFFFFh)
    - System BIOS Area (F0000hFFFFFh)
  - 623.5.22 FDHCFixed DRAM Hole Contr ol Regi ster (Device 0)
  - 633.5.23 SMRAMSystem Management RAM Control Register (Device 0)
  - 643.5.24 ESMRAMCExtended System Mgmt RAM Control Register (Device 0)
  - 653.5.25 ACAPIDAGP Capability Identifier Register (Device 0)
  - 663.5.26 AGPSTATAGP Status Register (Device 0)
  - 673.5.27 AGPCMDAGP Command Register (Device 0)
  - 683.5.28 AGPCTRLAGP Control Register (Device 0)
  - 693.5.29 APSIZEAperture Size (Device 0)
  - 703.5.30 ATTBASEAperture Translation Table Base Register (Device 0)
  - 713.5.31 AMTTAGP Interface Multi-Transaction Timer Register (Device 0)
  - 723.5.32 LPTTAGP Low Priority Transaction Timer Register (Device 0)
  - 733.5.33 TOMTop of Low Memory Register (Device 0)
  - 743.5.34 MCHCFGMCH Configuration Register (Device 0)
  - 753.5.35 ERRSTSError Status Register (Device 0)
  - 763.5.36 ERRCMDError Command Register (Device 0)
  - 783.5.37 SMICMDSMI Command Register (Device 0)
  - 3.5.38 SCICMDSCI Command Register (Device 0)
  - 793.5.39 SKPDScratchpad Data Register (Device 0)
  - 3.5.40 CAPIDProduct Specific Capability Identifier Register (Device 0)
- 803.6 Bridge Registers (Device 1)
  - 813.6.1 VID1Vendor Identificati on Regi ster (Device 1)
  - 3.6.2 DID1Device Identification Register (Device 1)
  - 823.6.3 PCICMD1PCI-PCI Command Register (Device 1)
  - 833.6.4 PCISTS1PCI-PCI Status Register (Device 1)
  - 843.6.5 RID1Revision Identification Register (Device 1)
  - 3.6.6 SUBC1Sub-Class Code Register (Device 1)
  - 3.6.7 BCC1Base Class Code Register (Device 1)
  - 853.6.8 MLT1Master Latency Timer Register (Device 1)
  - 3.6.9 HDR1Header Type Register (Device 1)
  - 3.6.10 PBUSN1Primary Bus Number Register (Device 1)
  - 863.6.11 SBUSN1Secondary Bus Number Register (Device 1)
  - 3.6.12 SUBUSN1Subordi nate Bus Number Register (Device 1)
  - 873.6.13 SMLT1Secondary Master Latency Timer Register (Device 1)
  - 883.6.14 IOBASE1I/O Base Address Register (Device 1)
  - 3.6.15 IOLIMIT1I/O Limit Address Register (Device 1)
  - 893.6.16 SSTS1Secondary PCI-PCI Status Register (Device 1)
  - 903.6.17 MBASE1Memory Base Address Register (Device 1)
  - 3.6.18 MLIM IT1Memory Limit Address Register (Device 1)
  - 913.6.19 PMBASE1Prefetchable Memory Base Address Register (Device 1)
  - 3.6.20 PMLIMIT1Prefetchable Memory Limit Address Register (Device 1)
  - 923.6.21 BCTRL1PCI-PCI Bridge Control Register (Device 1)
  - 933.6.22 ERRCMD1Error Command Register (Device 1)
  - 943.6.23 DWTCDRAM Write Ther mal Management Control Register (Device 1)
  - 953.6.24 DRTCDRAM Read Thermal Management Control Register (Device 1)
974 System Address Map
- 4.1 Memory Address Ranges
  - 98System Address Map
  - 98 Intel 82845 MCH for SDR Datasheet
  - Figure 4. DOS Compatible Area Address Map
  - Figure 5. Extended Memory Range Address Map
  - 994.1.1 VGA and MDA Memory Space
  - 1004.1.2 PAM Memory Spaces
  - 4.1.3 ISA Hole Memory Space
  - 1014.1.4 TSEG SMM Memory Space
  - 4.1.5 IOAPIC Memory Space
  - 4.1.6 System Bus Interrupt APIC Memory Space
  - 4.1.7 High SMM Memory Space
  - 4.1.8 AGP Aperture Space (Device 0 BAR)
  - 4.1.9 AGP Memory and Prefetchable Memory
  - 4.1.10 Hub Interface Subtractive Decode
- 1024.2 AGP Memory Address Ranges
  - 4.2.1 AGP DRAM Graphics Aperture
- 1034.3 System Management Mode (SMM) Memory Range
  - 1044.3.1 SMM Space Definition
  - 4.3.2 SMM Space Restrictions
- 1054.4 I/O Address Space
- 4.5 Intel MCH Decode Rules and Cross-Bridge Address Mapping
  - 4.5.1 Hub Interface Decode Rules
  - 1064.5.2 AGP Interface Decode Rules
    - Cycles Initiated Using AGP FRAME# Protocol
    - Cycles Initiated Using AGP PIPE# or SB Protocol
    - AGP Accesses to MCH that Cross Device Boundaries
1075 Functional Description
- 5.1 System Bus
  - 5.1.1 Dynamic Bus Inversion
  - 1085.1.2 System Bus Interrupt Delivery
  - 5.1.3 Upstream Interrupt Messages
- 1095.2 System Memory Interface
  - 5.2.1 Single Data Rate (SDR) SDRAM Interface Overview
  - 5.2.2 Memory Organization and Configur ation
    - 1105.2.2.1 Configuration Mechanism For DIMMs
      - Memory Detection and Initialization
      - SMBus Configuration and Access of the Serial Presence Detect Ports
      - Memory Register Programming
  - 1115.2.3 Memory Address Translation and Decoding
  - 5.2.4 DRAM Performance Description
    - 5.2.4.1 Data Integrity (ECC)
- 1125.3 AGP Interface Overview
  - 5.3.1 AGP Target Operations
  - 1145.3.2 AGP Transaction Ordering
  - 5.3.3 AGP Signal Levels
  - 5.3.4 4x AGP Protocol
  - 5.3.5 Fast Writes
  - 1155.3.6 AGP FRAME# Transactions on AGP
    - MCH Initiator and Target Operations
    - MCH Retry/Disconnect Conditions
    - Delayed Transaction
- 1175.4 Power and Thermal Management
  - 5.4.1 Processor Power State Control
  - 5.4.2 Sleep State Control
- 1185.5 Intel MCH Clocking
- 5.6 Intel MCH System Reset and Power Sequencing
1196 Electrical Characteristics
- 6.1 Absolute Maximum Ratings
- 6.2 Power Characteristics
- 1206.3 Signal Groups
  - Electrical Characteristics
  - 122 Intel 82845 MCH for SDR Datasheet
- 1226.4 DC Characteristics
  - Table 21. DC Characteristics
  - 123 Electrical Characteristics
  - Intel 82845 MCH for SDR Datasheet 123
1257 Ballout and Package Information
- 126Ballout and Package Information
- 126 Intel 82845 MCH for SDR Datasheet
- Figure 6. Intel 82845 MCH Ballout Diagram (Top ViewLeft Side)
- 127 Ballout and Package Information
- Intel 82845 MCH for SDR Datasheet 127
- Figure 7. Intel 82845 MCH Ballout Diagram (Top ViewRight Side)
- 128Ballout and Package Information
- 128 Intel 82845 MCH for SDR Datasheet
- Table 22. Intel 82845 MCH Ballout Listed Alphabetically by Signal Name
- 1347.1 Package Mechanical Information
  - 135 Ballout and Package Information
  - Intel 82845 MCH for SDR Datasheet 135
  - Figure 9. Intel MCH FC-BGA Package Dimensions (Bottom View)
1378 Testability
- 8.1 XOR Test Mode Initialization
- 1388.2 XOR Chains
  - 140Testability
  - 140 Intel 82845 MCH for SDR Datasheet
  - Table 24. XOR Chain 1
  - 141 Testability
  - Intel 82845 MCH for SDR Datasheet 141
  - Table 25. XOR Chain 2
  - 142Testability
  - 142 Intel 82845 MCH for SDR Datasheet
  - Table 26. XOR Chain 3
  - 143 Testability
  - Intel 82845 MCH for SDR Datasheet 143
  - Table 27. XOR Chain 4
  - 144Testability
  - 144 Intel 82845 MCH for SDR Datasheet
  - Table 28. XOR Chain 5
  - 146Testability
  - 146 Intel 82845 MCH for SDR Datasheet
  - Table 29. XOR Chain 6
  - 147 Testability
  - Intel 82845 MCH for SDR Datasheet 147
  - Table 30. XOR Chain 7

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