Intel 845 manual I/O Mapped Registers, CONFADDR-Configuration Address Register

Register Description

R

Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONF_ADDR is non-zero, and is less than the value in the Host-AGP device’s Secondary Bus Number register, or greater than the value in the Host-AGP device’s Subordinate Bus Number register, the MCH will generate a Type 1 hub interface configuration cycle. The ICH2 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle is meant for Primary PCI, or a downstream PCI bus.

AGP Configuration Mechanism

From the chip-set configuration perspective, AGP is seen as a PCI bus interface residing on a Secondary Bus side of the “virtual” PCI-PCI bridges referred to as the MCH Host-AGP bridge. On the Primary Bus side, the “virtual” PCI-PCI bridge is attached to PCI Bus 0. Therefore, the Primary Bus Number register is hardwired to 0. The “virtual” PCI-PCI bridge entity converts Type 1 PCI bus configuration cycles on PCI Bus 0 into Type 0 or Type 1 configuration cycles on the AGP interface. Type 1 configuration cycles on PCI Bus 0 that have a Bus Number that matches the Secondary Bus Number of the MCH’s “virtual” Host-to-PCI_B/AGP bridge will be translated into Type 0 configuration cycles on the AGP interface.

If the Bus Number is non-zero, greater than the value programmed into the Secondary Bus Number Register, and less than or equal to the value programmed into the Subordinate Bus Number Register, the MCH will generate a Type 1 PCI configuration cycle on AGP.

3.3I/O Mapped Registers

The MCH contains two registers that reside in the processor I/O address space: the Configuration Address (CONF_ADDR) register and the Configuration Data (CONF_DATA) register. The Configuration Address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window.

3.3.1CONF_ADDR—Configuration Address Register

I/O Address:	0CF8h Accessed as a DWord
Default Value:	00000000h
Access:	R/W
Size:	32 bits

CONF_ADDR is a 32 bit register that can be accessed only as a DWord. A Byte or Word reference will "pass through" the Configuration Address register and the hub interface, onto the PCI bus as an I/O cycle. The CONF_ADDR register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.

34 Intel® 82845 MCH for SDR Datasheet