Signal Description
R
Intel® 82845 MCH for SDR Datasheet 21
Signal Name Type Description
ADS# I/O
AGTL+ Address Strobe: The system bus owner asserts A DS # to indicate the first
of two cycles of a request phase.
BNR# I/O
AGTL+ Block Next Request: BNR# is us ed t o block the current request bus
owner from issuing a new request. This signal dynamically controls the
system bus pipeline depth.
BPRI# O
AGTL+ Bus Priority Request: The MCH is the only Priority A gent on t he system
bus. It asserts this signal to obtain the ownership of the address bus. This
signal has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK#
signal was asserted.
BR0# I/O
AGTL+ Bus Request 0#: The MCH pulls the proces s or bus BR0# signal low
during CPURST#. The signal is sampled by the processor on the active-to-
inactive transition of CPURST#. The minimum setup time f or this signal is
4 BCLKs. The minimum hold time is 2 BCLKs and the maximum hol d t ime
is 20 BCLKs. BR0# should be three-stated after the hold time requirement
has been satisfied.
CPURST# O
AGTL+ Processor Reset: The CPURST# pin is an out put from the MCH. The
MCH asserts CPURST# while RSTIN# (PCIRST# from the ICH2) is
asserted and for approximately 1 ms after RSTIN# is deasserted. The
CPURST# allows the processor to begin execution in a known state.
DBSY# I/O
AGTL+ Data Bus Busy: DBSY# is used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
DEFER# O
AGTL+ Defer Response: This signal, when asserted, indic ates that the MCH will
terminate the transaction currently being snooped with either a deferred
response or with a retry response.
DBI[3:0]# I/O
AGTL+ Dynamic Bus Inversion: DBI[3:0]# are dri ven al ong with t he HD[ 63:0]#
signals. DBI[3:0]# Indicate if the associated data signals are inverted.
DBI[3:0]# are asserted such that the number of data bits driven electrical l y
low (low voltage) within the corresponding 16-bit group never exceeds 8.
DBI[x]# Data Bits
DBI3# HD[63:48]#
DBI2# HD[47:32]#
DBI1# HD[31:16]#
DBI0# HD[15:0]#
DRDY# I/O
AGTL+ Data Ready: Asserted for each cycl e t hat data is transferred.
HA[31:3]# I/O
AGTL+ Host Address Bus: HA[31:3]# connect to the s ystem address bus. During
processor cycles, HA[31:3]# are inputs. The MCH drives HA[31:3]# during
snoop cycles on behalf of the hub interface and AGP/Secondary PCI
initiators. HA[31:3]# are transferred at 2x rate. Note that the address is
inverted on the system bus.
HADSTB[1:0]# I/O
AGTL+ Host Address Strobe: The source synchronous strobes us ed to transfer
HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
Strobe Address Bits
HADSTB0# HA[16:3]#, HREQ[4:0]#
HADSTB1# HA[31:17]#